Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2002-01-09
2004-04-20
Mengistu, Amare (Department: 2673)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S066000
Reexamination Certificate
active
06724357
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a surface discharge plasma display panel (PDP) and, more particularly, to an apparatus and method for driving a surface discharge PDP which control the slope of an erasing pulse to perform the initialization operation in sub-field periods of driving frames.
2. Description of the Related Art
Generally, a surface discharge plasma display panel (referred to as ‘display panel’ hereinafter) is a light emitting device which excites a fluorescent material placed inside discharge cells thereof, to thereby display images. It is compact, manufactured through simple fabrication processes and easily realized in a large screen so that it is widely used as a bulletin board of a stock exchange, a display for video conferencing and a wide-screen wall-hanged TV.
FIG. 1
roughly illustrates a general circuit for driving the surface discharge PDP. In
FIG. 1
, reference numeral
10
represents a color three-electrode surface discharge PDP with resolution LxK constructed in a manner that first L sustain electrodes X
1
~X
L
and second L sustain electrodes Y
1
~Y
L
are alternately arranged in parallel with each other, K address electrodes A
1
~A
K
intersect the first and second sustain electrodes X
1
~X
L
and Y
1
~Y
L
, having predetermined spaces therebetween, and cells S are formed at intersections where the first and second L sustain electrodes X
1
~X
L
and Y
1
~Y
L
intersect the K address electrodes A
1
~A
K
, to construct the entire screen of LxK R (red), G (green) and B (blue) cells in a matrix form. Here, the first L sustain electrodes X
1
~X
L
are connected in parallel by a first common sustain electrode.
Reference number
20
in
FIG. 1
denotes an X-electrode driver connected to the first sustain electrodes X
1
~X
L
of the panel
10
to provide a driving pulse to them, and
30
represents an Y-electrode driver connected to the second sustain electrodes Y
1
~Y
L
, of the panel
10
to supply a driving pulse to them. In addition, reference numeral
40
represents an address driver connected to the address electrodes A
1
~A
K
of the panel
10
to selectively apply a driving pulse to them based on a digital video signal corresponding to each cell S. Reference numeral
50
denotes a system controller which digitalizes an analog video signal IMAGE supplied from the outside to output a digital video signal, and provides various control signals to the X-electrode driver
20
, Y electrode driver
30
and address driver on the basis of the digital video signal and various external signals (clock (CLK), horizontal synchronous signal (HS) and vertical synchronous signal (VS)).
FIG. 2
is a cross-sectional view of the cell S in FIG.
1
. Referring to
FIG. 2
, an upper glass
11
and a lower glass
14
placed opposite to the upper glass
11
having a predetermined distance therebetween are combined with each other to construct a predetermined discharge space, that is, the discharge cell. The upper glass
11
is constructed in a manner that a first sustain electrode X and a second sustain electrode Y are formed thereon in parallel with each other, a dielectric layer
12
that restricts discharge current when discharge occurs and facilitates generation of wall charges is formed on the first and second sustain electrodes X and Y, and a MgO protection layer
13
for protecting the first and second sustain electrodes X and Y and the dielectric layer
12
from sputtering during discharge is formed on the dielectric layer
12
. The lower glass
14
is constructed in such a manner that an address electrode A is formed on the plane opposite to the upper glass
11
, first and second barriers
15
a
and
15
b
for preventing color mixture between cells and securing the discharge space are formed at both sides of the address electrode A in parallel therewith, and a fluorescent material
16
is coated on the address electrode A and parts of the first and second barriers.
The basic operation of the cell constructed as above is explained below with reference to
FIGS. 3 and 4
.
In the display panel, generally, the span of time for displaying one image is divided into a plurality of frames F
1
~F
n
as shown in FIG.
3
(A), each frame F being split into a plurality of sub-fields SF
1
~SF
M
as shown in FIG.
3
(B). In case of realization of 256 gray scales, for instance, one frame F is constructed of eight sub-fields SF
1
~SF
8
to provide signals of the display panel. Each sub-field SF includes an initialization period, a data addressing period and a sustaining period, as shown in FIG.
3
(C), to be provided with a predetermined signal.
That is, the sub-field SF applies a voltage with a predetermined level, 70V, for example, to the address electrode A first, and supplies the high voltage writing pulse of 400V, for example, to the first sustain electrode X during a period (a), as shown in FIG.
4
. Here, cells S which were written or not written in the previous sub-field perform discharge according to the high voltage. At this time, excessive wall charges in the cells S formed by the high voltage generate self-erase discharge due to inner wall charges after falling of a writing pulse. Accordingly, negative wall charges are created in the first sustain electrode X and positive wall charges are formed in the second sustain electrode Y.
Subsequently, a predetermined erasing pulse is applied to the second sustain electrode Y while voltages of the address electrode A and the first sustain electrode X being set to a predetermined level, 0V, during periods (b) and (c). This erases the wall charges formed in the second sustain electrode Y during the period (a). That is, a small amount of negative wall charges formed in the first sustain electrode X and a small quantity of positive wall charges created in the second sustain electrode Y are neutralized in the discharge space according to the erasing pulse applied to the second sustain electrode Y, to thereby remove the wall charges remaining in the cell S.
Through the aforementioned initialization operation, electron and wall charge components formed in the first and second sustain electrodes X and Y of the cell S are cleared, and then 70V, for example, is applied to the address electrode A, 50V, for example, is applied to the first sustain electrode X, and a reverse voltage (negative voltage) with a predetermined level is applied to the second sustain electrode Y, to perform data addressing operation through the address electrode A. Here, discharge for data addressing occurs in the address electrode, first and second sustain electrodes X and Y. At this time, discharge of the first and second sustain electrodes X and Y is facilitated according to charged particles in the discharge space so that generation of secondary discharge forms negative wall charges in the first sustain electrode X and positive wall charges in the second sustain electrode Y, during a period (d).
Subsequently, the voltages of the address electrode A, first and second sustain electrodes X and Y are set to 0V, for instance, at a point of time when the data addressing period of the sub-field SF is finished, and a predetermined positive voltage is applied to the second sustain electrode Y, to generate discharge caused by the positive wall charges in the cell S, created in the second sustain electrode Y during the data addressing period (d) and the voltage applied from the outside in the first electrode X during a period (e). That is, a predetermined sustaining pulse is applied to the second sustain electrode Y.
After supply of the sustaining pulse to the second sustain electrode Y, as described above, a predetermined positive voltage is provided to the first sustain electrode X to discharge the positive wall charges formed in the first sustain electrode X to the second sustain electrode Y. In other words, a predetermined sustaining pulse is applied to the first sustain electrode X during a period (f).
Thereafter, the operations (e) and (f) are alternately performed during the sustaining period of the sub
Chae Gyun
Kim Bong Chool
Lilling & Lilling P.C.
Mengistu Amare
UPD Corporation
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