Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1998-11-05
2003-07-08
Shalwala, Bipin (Department: 2673)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S087000, C345S100000, C349S151000
Reexamination Certificate
active
06590551
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to an apparatus and method for driving a liquid crystal display (LCD) and, more particularly, to an apparatus and method for driving scanning lines formed in the LCD panel.
2. Description of Background Art
Generally, a conventional LCD apparatus controls the light transmissivity of liquid crystal in the liquid crystal panel based on the voltage level of video signals applied to the liquid crystal panel to display images. The liquid crystal panel includes liquid crystal cells arranged in a matrix pattern, and control switches for selectively applying the video signals to each liquid crystal cell. The control switches are formed with thin film transistors (TFTs) with their sources and drains formed in an alternating pattern. Often during the fabrication process of the liquid crystal panel, the TFTs are misaligned, causing them to have different parasitic capacitances. The differences in the parasitic capacitance between the TFTs distort tile video signals applied to tile liquid crystal cells, causing undesirable flickers in the picture being displayed by the liquid crystal panel.
FIG. 1A
shows a schematic view of such a conventional liquid crystal panel having a delta structure. As shown therein, the conventional liquid crystal panel includes a plurality of odd-numbered scanning lines
4
′, a plurality of even-numbered scanning lines
4
″ formed between the odd-numbered scanning lines
4
′, and a plurality of data lines
2
crossing the scanning lines
4
′ and
4
″. Each of the odd-numbered scanning lines
4
′ is connected to a plurality of first TFTs (odd-numbered TFTs)
8
A arranged in a row, and each of the even-numbered scanning lines
4
″ is connected to a plurality of second TFTs (even-numbered TFTs)
8
B arranged in another row. Each of the TFTs
8
A and
8
B is connected to a liquid crystal cell (or pixel electrode
6
). Each of the first TFTs
8
A is turned on and off based on a scanning pulse applied through the corresponding scanning line
4
′ connected to the first TFTs
8
A. Each of the second TFTs
8
B is turned on and off based on a scanning pulse applied through the corresponding scanning line
4
″ connected to the second TFT
8
B.
By turning on the first TFT
8
A, a current path between the corresponding data line
2
connected to the TFT
8
A and the corresponding liquid crystal cell
6
is established, and by turning on the second TFT
8
B, a current path between the corresponding data line
2
connected to the TFT
8
B and the corresponding liquid crystal cell
6
is established. Through the established current paths, data signals from the data lines
2
are applied to the corresponding TFTs
8
A and
8
B. The sources and drains of the first or second TFTs
8
A or
8
B are simultaneously formed using a same fabrication process, and their formation positions can vary with respect to the corresponding gate.
FIG. 1B
shows an enlarged view of portion
1
B shown in FIG.
1
A. As shown in
FIG. 1B
, an active region AR partially overlaps the source ST, the drain DT and the gate GT of each TFT
8
A or
8
B to establish first and second parasitic capacitors Cgs and Cgd. The first parasitic capacitor Cgs emerges between the gate GT and the source ST while the second parasitic capacitor Cgd emerges between the gate GT and the drain DT of the TFT
8
A or
8
B. The characteristic of the parasitic capacitors Cgs and Cgd can differ substantially from each other depending on the exact positions of the source ST and the drain DT moved. For example, the parasitic values of the capacitors Cgs and Cgd differ from each depending on the position of the TFTs and the exact position of the source ST and the drain DT. For instance, if all the sources ST and the drains DT of the TFTs
8
A and
8
B are misaligned to the right from the original or predetermined position when they are formed, the first parasitic capacitor Cgs of the odd-numbered TFTs
8
A has a larger capacitance value than the first parasitic capacitor Cgs of the even-numbered TFTs
8
B, while the second parasitic capacitor Cgd of the odd-numbered TFTs
8
A has a smaller capacitance value than the second parasitic capacitor Cgd of the even-numbered TFTs
8
B. On the contrary, if the sources ST and the drains DT are misaligned to the left from the desired position, the first parasitic capacitor Cgs of the odd-numbered TFTs
8
A has a smaller capacitance value than the first parasitic capacitor Cgs of the even-numbered TFTs
8
B, while the second parasitic capacitor Cgd of the odd-numbered TFTs
8
A has a larger capacitance value than the second parasitic capacitor Cgd of the even-numbered TFTs
8
B.
The second parasitic capacitors Cgd do not directly influence the liquid crystal cells
6
; however, the first parasitic capacitors Cgs vary the voltage level of video signals applied to the liquid crystal cells
6
. This occurs because, as shown in
FIG. 2A
, the first parasitic capacitor Cgs is serially connected to a parallel circuit
6
a
of the corresponding liquid crystal cell
6
having a support capacitor Cst. The serial connection of the first parasitic capacitor Cgs lowers the voltage level of the corresponding liquid crystal cell
6
at the time the corresponding TFT is turned off.
Specifically, as shown in
FIG. 2B
, the TFT (
8
A or
8
B) is turned on when a high level voltage (Vgh) of the scan signal SS is applied to the TFT through the corresponding scanning line
4
. As the TFT is turned on, a video signal VD on the corresponding data line
2
is applied to the corresponding liquid crystal cell
6
and the support capacitor Cst. At this time, the voltage Vd of the video signal VD is charged into the liquid crystal cell
6
and the support capacitor Cst, and the voltage difference between the high level voltage Vgh and the video signal voltage Vd is charged to the first parasitic capacitor Cgs. When the scan signal SS transits from the high level voltage Vgh to a low level voltage Vgl, the TFT
8
is turned off to disconnect the current path from the data line
2
to the liquid crystal cell
6
and the support capacitor Cst. Then the first parasitic capacitor Cgs suddenly discharges the charged voltage into the corresponding scanning line
4
and, simultaneously, is charged by the voltage from the liquid crystal cell
6
and the support capacitor Cst. As a result, the voltage charged in the liquid crystal cell
6
is instantaneously reduced. By such a charge and discharge operation of the parasitic capacitor Cgs, an output signal CLS of the liquid crystal cell
6
sharply decreased by a predetermined voltage &Dgr;Vp from the video signal voltage Vd as shown in FIG.
2
B. The drop voltage &Dgr;Vp in the output signal CLS of the liquid crystal cell
6
can be expressed as follows:
Δ
Vp2
=
(
Cgs
)
(
Vg
)
Clc
+
Cst
+
Cgs
(
1
)
wherein Vg represents a voltage difference between the high level voltage Vgh and the low level voltage Vgl of the scan signal SS, and Clc represents a capacitance value of the corresponding liquid crystal cell
6
. Since the drop voltage &Dgr;Vp changes in accordance with the capacitance value of the parasitic capacitor Cgs as seen from the above equation (1), the drop voltage &Dgr;Vp in the output of the liquid crystal cell
6
connected to odd-numbered TFT
8
A and the drop voltage &Dgr;Vp in the output of the liquid crystal cell
6
connected to even-numbered TFT
8
B differ from each other when misalignment occurs during the fabrication of the TFTs
8
A and
8
B.
For example, if the overlapped width of the source ST and the active region AR is set to be 3 &mgr;m, but the position of the source ST formed on the substrate is shifted to the left by 1 &mgr;m due to misalignment, the source ST and the active region AR of each odd-numbered TFT
8
A are overlapped by 2 &mgr;m while the source ST and the active region AR of each even-numbered TFT
8
B are overlapped by 4 &mgr;m. If the video signal VD has an intermediate gray level vol
LG Electronics Inc.
Said Mansour M.
Shalwala Bipin
LandOfFree
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