Electric lamp and discharge devices: systems – Plural power supplies – Plural cathode and/or anode load device
Reexamination Certificate
2002-10-16
2004-01-20
Clinger, James (Department: 2821)
Electric lamp and discharge devices: systems
Plural power supplies
Plural cathode and/or anode load device
C315S169400, C345S060000, C345S068000
Reexamination Certificate
active
06680581
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an apparatus and a method for driving a plasma display panel (PDP). More specifically, the present invention relates to an apparatus and a method for driving a PDP, where a switch device can perform zero voltage switching in driving the PDP.
2. Description of the Related Art
In general, a PDP is a flat plate display for displaying characters or images using plasma generated by gas discharge. Pixels ranging from hundreds of thousands to more than millions are arranged in the form of a matrix according to the size of the PDP. PDPs are divided into direct current (DC) PDPs and alternating current (AC) PDPs according to the shape of the waveform of an applied driving voltage and the structure of a discharge cell.
The most significant difference between the DC PDP and the AC PDP lies in that current directly flows in discharge spaces while a voltage is applied in the DC PDP, because electrodes are exposed to the discharge spaces. Therefore, a resistor for restricting the current must be used outside of the DC PDP. On the other hand, in the case of the AC PDP, the current is restricted due to the natural formation of capacity because a dielectric layer covers the electrodes. The AC PDP has a longer life than the DC PDP because the electrodes are protected against the shock caused by ions during discharge. A memory characteristic that is one of the important characteristics of the AC PDP is caused by the capacity due to the dielectric layer that covers the electrodes.
According to the light emission principle of the AC PDP, discharge occurs because an electric potential difference in the form of a pulse is formed in common electrodes (X electrodes) and scan electrodes (Y electrodes). As such, vacuum ultraviolet (UV) rays generated in a discharge process are excited to red R, green G, and blue B fluorescent bodies. The respective fluorescent bodies emit light due to light combination.
In the AC PDP, because the X electrodes and the Y electrodes for sustaining discharge operate as capacitive loads, capacitance C
p
with respect to the X and Y electrodes exists. Reactive power other than power for discharge is necessary in order to apply waveforms for the sustain-discharge. A circuit for recovering and re-using the reactive power is referred to as a sustain-discharge circuit, or a power recovery circuit.
According to the method for driving the panel by the X and Y electrode driving circuits, a frame consists of n sub-fields. A sub-field consists of a reset period, a scan period, a sustain period, and an erase period.
In the reset period, the address electrodes A
1
through A
m
and the X electrodes are sustained to be at 0 V in the first half thereof. A voltage of more than a discharge starting voltage to a voltage of no more than the discharge starting voltage with respect to the sustain electrodes is applied to the Y electrodes. In the latter half of the reset period, the voltage of no more than the discharge starting voltage with respect to the sustain electrodes is applied to the scan electrodes. In the scan period, the scan electrodes are sustained to be at a scan voltage. A positive scan pulse voltage and a scan pulse voltage (0 V) are simultaneously applied to the address electrode corresponding to the discharge cell to be displayed in the first line among addressing electrodes and the scan electrode in the first line, respectively, so that the wall charge is accumulated. In the sustain period, a predetermined sustain pulse is applied to the scan and sustain electrodes so that the sustain-discharge occurs in gray scales to be displayed in the discharge cells. In the erase period, a predetermined erase pulse is applied to the sustain electrodes so that the sustain-discharge is stopped.
Driving of the sustain-discharge circuit of a conventional AC PDP will now be described with reference to
FIGS. 1A and 1B
that show a conventional sustain-discharge circuit and the operation waveforms of the conventional sustain-discharge circuit.
As shown in
FIG. 1A
, the sustain-discharge circuit suggested by L. F. Weber and disclosed in the U.S. Pat. Nos. 4,866,349 and 5,081,400, is the sustain-discharge circuit or the power recovery circuit of the AC PDP. In the driving circuit of the AC PDP, a sustain-discharge circuit
10
of the X electrodes has the same structure as that of a sustain-discharge circuit
11
(not shown in detail) of the Y electrodes. The sustain-discharge circuit of the X electrodes will now be described for sake of convenience.
The conventional sustain-discharge circuit
10
includes a power recovery unit comprising two switches S
1
and S
2
, two diodes D
1
and D
2
, and a power recovery capacitor C
c
and a sustain-discharge unit comprising two serially connected switches S
3
and S
4
. An inductor L
c
is connected between the diodes D
1
and D
2
of the power recovery unit and the two switches S
3
and S
4
of the sustain-discharge unit. A load having a capacitor C
p
of the PDP is connected to the sustain-discharge unit. At this juncture, a parasitic device is not displayed.
The conventional sustain-discharge circuit having the above structure operates in four modes according to the switching sequence operations of the switches S
1
through S
4
, as shown in FIG.
1
B. The waveforms of the current I
L
that flows through an output voltage V
p
and the inductor L
c
are respectively shown according to the switching sequence operations.
In an initial stage, the panel both-end voltage is sustained to be 0 V because the switch S
4
is made to turn on just before the switch S
1
is made to turn on. As such, the power recovery capacitor C
c
is previously charged by a voltage V
s
/2 that is half of an external applied voltage V
s
so that a rush current is not generated when the sustain-discharge starts.
In a state where the panel both-end voltage V
p
is sustained to be 0 V, at the point of time t
0
, the operation of a mode
1
where the switch S
1
is turned on and the switches S
2
, S
3
, and S
4
are turned off, starts.
In the operation periods between t
0
and t
1
of the mode
1
, an LC resonance circuit is formed through the channel of the power recovery capacitor C
c
, the switch S
1
, the diode D
1
, the inductor L
c
, and the plasma panel capacitor C
p
. Therefore, the current I
L
flows through the inductor L
c
and the output voltage V
p
of the panel increases.
As shown in
FIG. 1B
, the current I
L
that flows through the inductor L
C
slowly decreases due to parasitic resistance (not shown) and becomes 0 at the point of time t
1
. The output voltage V
p
of the panel becomes the external applied voltage V
s
.
When the mode
1
is completed, a mode
2
, where the switches S
1
and S
3
are turned on and the switches S
2
and S
4
are turned off, starts. In the operation period between t
1
and t
2
of the mode
2
, the external applied voltage V
s
directly flows through the panel capacitor C
p
through the switch S
3
, to thus sustain the output voltage V
p
of the panel.
When the mode
2
is completed in a state where the discharge of the output voltage V
p
of the panel is sustained, a mode
3
, where the switch S
2
is turned on and the switches S
1
, S
3
, and S
4
are turned off, starts.
In the operation period between t
2
and t
3
of the mode
3
, the LC resonance circuit is formed through the channel reverse to that in the mode
1
, that is, through the channel of the plasma panel capacitor C
p
, the inductor L
c
, the diode D
1
, the switch S
2
, and the power recovery capacitor C
c
. Accordingly, as shown in
FIG. 1B
, the current I
L
flows through the inductor L
c
and the output voltage V
p
of the panel decreases. Therefore, the current I
L
of the inductor L
c
and the output voltage V
p
of the panel become 0 at the point of time t
3
.
In the operation period between t
3
and t
4
of a mode
4
, the switches S
2
and S
4
are turned on and the switches S
1
and S
3
are turned off. Accordingly, the output voltage V
p
of the panel is sustained to be 0 V.
An Byung-Nam
Lee Jun-Young
Park Jung-Pil
Alemu Ephrem
Clinger James
McGuireWoods LLP
Samsung SDI & Co., Ltd.
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