Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2005-11-08
2005-11-08
Tran, Michael (Department: 2827)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185020
Reexamination Certificate
active
06963504
ABSTRACT:
In a passive element memory array, such as a rail stack array having a continuous semiconductor region along one or both of the array lines, programming a memory cell may disturb nearby memory cells as result of a leakage path along the array line from the selected cell to the adjacent cell. This effect may be reduced substantially by changing the relative timing of the programming pulses applied to the array lines for the selected memory cell, even if the voltages are unchanged. In an exemplary three-dimensional antifuse memory array, a positive-going programming pulse applied to the anode region of the memory cell preferably is timed to lie within the time that a more lightly-doped cathode region is pulsed low.
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Knall N. Johan
Scheuerlein Roy E.
Matrix Semiconductor Inc.
Tran Michael
Zagorin O'Brien Graham LLP
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