Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2003-03-31
2004-11-23
Tran, M. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S225700
Reexamination Certificate
active
06822903
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to high-density semiconductor memory arrays and, in preferred embodiments, the invention particularly relates to monolithic three-dimensional antifuse memory arrays utilizing rail stacks.
BACKGROUND
Recently there has been an interest in fabricating memories having memory cells disposed at numerous levels above a substrate. Each level includes a plurality of spaced-apart first lines extending in one direction, which lines are vertically separated from a plurality of parallel spaced-apart second lines in a second direction, for example, extending perpendicular to the first lines. Memory cells are disposed between the first lines and second lines at the intersections (or the projection thereof) of these lines.
Exemplary memory arrays are described, for example, in U.S. Pat. Nos. 5,835,396 and 6,034,882, which describe a pillar style of memory cell, each formed between an associated first array line and an associated second array line. Characteristic of such pillar style memory cells is the separation of the various structures forming each cell from similar structures forming adjacent cells.
Another way of fabricating three-dimensional memory arrays departs from the structures shown in these patents and uses “rail-stacks” to form the memory cells. A rail stack is formed by creating successive layers of material, which are then etched together to form an aligned stack of layers. A memory cell may be formed at the intersection of two such rail stacks. Fabricating a memory array using rail stacks frequently requires fewer mask layers (and processing steps) to implement the array.
Exemplary memory arrays utilizing rail stacks are described in U.S. patent application Ser. No. 09/560,626 by N. Johan Knall, filed Apr. 28, 2000, which application describes a memory employing antifuses where a diode is formed upon programming a particular bit. In this connection see, “
A Novel High
-
Density Low
-
Cost Diode Programmable Read Only Memory
,” by de Graaf, Woerlee, Hart, Lifka, de Vreede, Janssen, Sluijs and Paulzen, IEDM-96, beginning at page 189 and U.S. Pat. Nos. 4,876,220; 4,881,114 and 4,543,594.
SUMMARY
In a passive element memory array, such as a rail stack array having a continuous semiconductor region along one or both of the array lines, we have observed that the programming of a memory cell may cause the unintentional programming of an adjacent memory cell. This is believed to be caused by a leakage path through the continuous semiconductor region from the selected cell to the adjacent cell. In an exemplary antifuse rail stack array, for example, a lightly-doped n-type semiconductor region (i.e., n− region) is continuous along the array line connected to the cathode region of the memory cells. A leakage current through this n− region from a programmed antifuse memory cell to an adjacent unprogrammed memory cell can collapse the depletion region under the adjacent antifuse, causing voltage stress which can erroneously write the adjacent bit. Such an effect may be reduced or eliminated by forming memory cells using a pillar structure rather than a rail stack structure, but this increases processing steps and manufacturing cost.
We have discovered that this erroneous programming of adjacent memory cells may be reduced substantially by changing the relative timing of the programming pulses applied to the array lines for the selected memory cell, even if the voltages are unchanged. Using the above exemplary antifuse rail stack memory array, a positive-going programming pulse applied to the anode region of the memory cell preferably is timed to lie within the time that the more lightly-doped cathode region is low (by virtue of a negative-going programming pulse applied to the cathode). For example, in certain embodiments the array line associated with the anode region of the selected memory cell is preferably driven to its programming voltage after the array line associated with the cathode region of the selected memory cell has substantially reached its programming voltage, and the ‘anode’ array line is preferably driven back to its unselected voltage before the ‘cathode’ array line begins to be driven back to its unselected voltage.
In a broader method context, the invention provides a method for programming a memory array having at least one memory plane. The array includes memory cells coupled between an associated one of a respective plurality of array lines on each of two memory array layers, and includes memory cells having an anode region and a cathode region, one of the regions being configured to inject charge to the other region when forward biased. The method includes driving a first array line associated with the injecting region of a selected memory cell to a selected bias voltage for the first array line, and driving a second array line associated with the non-injecting region of the selected cell to a selected bias voltage for the second array line. The method includes then driving the first array line to an unselected bias voltage for the first array line, and driving the second array line to an unselected bias voltage for the second array line, wherein the first array line voltage transitions at least a first percentage toward its unselected bias voltage before the second array line transitions at most a second percentage toward its unselected bias voltage.
In some embodiments the memory array may be a three-dimensional array having at least three array line layers defining at least two memory planes. In some embodiments the memory array may include back-to-back memory cells, in which a given array line connects to either the anode or the cathode of memory cells in the memory planes above and below the array line. In other embodiments, the memory array may include serial chain memory cells, in which a given array line connects to one of the anode or the cathode of memory cells in the memory plane above the array line, and connects to the other of the anode or the cathode of memory cells in the memory plane below the array line.
The invention is useful for a variety of memory cells. In some embodiments the memory array may include antifuse memory cells. In certain other embodiments, the memory array may include fuse memory cells. In certain other embodiments, the memory array may include memory cells having a ferro-electric material (e.g., magneto-resistive (MRAM) memory cells). In certain other embodiments, the memory array may include memory cell including an organic layer.
In certain preferred embodiments the non-injecting region of a memory cell includes a lightly-doped semiconductor region formed along one of the array lines in a rail stack configuration, and the injecting region of a memory cell includes a more heavily doped semiconductor region. An antifuse layer may be formed between the injecting region and the non-injecting region.
The invention in several aspects is suitable for integrated circuits having a memory array, for memory cell and memory array structures, for methods for operating such integrated circuits and memory arrays, and for computer readable media encodings of such integrated circuits or memory arrays, all as described herein in greater detail and as set forth in the appended claims.
The foregoing is a summary and thus contains, by necessity, simplifications, generalizations and omissions of detail. Consequently, those skilled in the art will appreciate that the foregoing summary is illustrative only and that it is not intended to be in any way limiting of the invention. Other aspects, inventive features, and advantages of the present invention, as defined solely by the claims, may be apparent from the detailed description set forth below.
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patent: 4646266 (1987-02-01), Ovshinsky et al.
patent: 4868616 (1989-09-01), Johnson et al.
patent: 4876220 (1989-10-01), Mohsen et al.
patent: 4881114 (1989-11-01), Mohsen et al.
patent: 5301144 (1994-04-01), Kohno
patent: 5429968 (1995-07-01),
Knall N. Johan
Scheuerlein Roy E.
Matrix Semiconductor Inc.
Tran M.
Zagorin O'Brien & Graham LLP
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