Electrical computers and digital processing systems: processing – Processing architecture – Long instruction word
Reexamination Certificate
2008-04-29
2008-04-29
Pan, Daniel (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Long instruction word
C712S206000, C712S213000
Reexamination Certificate
active
10309295
ABSTRACT:
Apparatus and method for dispatching a very long instruction word (VLIW) instruction having a variable length are provided. The apparatus for dispatching a VLIW instruction includes a packet buffer for storing at least one or more VLIW instructions, and a decoding unit configured to constitute a VLIW instruction to be currently executed among the VLIW instructions stored in the packet buffer and decode predetermined bits of each sub-instruction contained in the VLIW instruction. The apparatus dispatches a corresponding sub-instruction to an FU which corresponds to each sub-instruction, based on the results of decoding performed in the decoding unit, position information on the sub-instructions that are placed on the packet buffer, and position information on the sub-instructions that are placed in the current VLIW instruction. Sub-instructions can be effectively dispatched to corresponding FUs using simple decoding logic even in a case where the length of the VLIW instruction is not fixed.
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English translation of JP 09-167093.
Bae Gun-young
Im Hyung-jun
Jeong Seh-woong
Kim Young-duck
Lim Kyoung-mook
F. Chau & Associates LLC
Pan Daniel
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