Coded data generation or conversion – Digital code to digital code converters – Unnecessary data suppression
Reexamination Certificate
2003-07-03
2004-10-19
Jeanglaude, Jean Bruner (Department: 2819)
Coded data generation or conversion
Digital code to digital code converters
Unnecessary data suppression
C348S441000
Reexamination Certificate
active
06806818
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an apparatus and method for digital stream conversion, and more particularly to an apparatus and method for digital stream conversion which outputs a digital stream having a packetized format at a rate which is slower than the input rate.
2. Description of the Background Art
Processing of various kinds of digital streams, e.g., a transport stream compliant with the MPEG2 (Moving Picture Experts Group 2) standard, may sometimes involve a process which purposely outputs an input digital stream at a slower rate than the rate at which the digital stream is inputted. Hereinafter, such a rate conversion process for a digital stream and an accompanying process of altering a portion of the data contained in the digital stream will together be referred to as a “stream conversion process”. Furthermore, an apparatus which performs a stream conversion process will be referred to as a “stream conversion apparatus”.
An example of a conventional stream conversion apparatus is an MPEG2 transport stream transfer rate conversion apparatus described in Japanese Patent Laid-Open Publication No. 11-205789 (see FIG.
13
). This apparatus receives, as an input stream
91
, an MPEG2 transport stream containing packets of a predetermined length. An MPEG2 transport stream typically includes packets which only contain invalid data (hereinafter referred to as “NULL packets”) and packets which contain program clock references (hereinafter referred to as “PCRs”) as defined under the MPEG2 system standard. A packet identifier for identifying the type of the packet is assigned to each packet in the input stream
91
.
The input stream
91
is inputted to a synchronization detection section
81
. The synchronization detection section
81
detects synchronization of the input stream
91
. Based on the packet identifier assigned to each inputted packet, a packet identification section
82
identifies the packet. More specifically, the packet identification section
82
deletes any NULL packets contained in the input stream
91
, and writes any other packets (herein after referred to as “non-NULL packets”) to a buffer
89
. The buffer
89
temporarily stores non-NULL packets.
Each time a non-NULL packet is outputted from the packet identification section
82
, a PCR extraction section
83
generates a write control signal
92
for the buffer
89
, and extracts a PCR
93
, if any, from the non-NULL packet. Based on the PCR
93
extracted by the PCR extraction section
83
, a PLL (Phase Locked Loop) circuit
84
generates a 27 MHz system clock, and outputs the PCR
94
obtained after the PLL (hereinafter referred to as a “post-PLL PCR”) to a PCR replacement section
87
.
A packet reading section
85
reads the packets stored in the buffer
89
, in synchronization with an externally-supplied output timing signal
95
. Among the packets which have been read, packets containing no PCRs are fed to an output section
88
, whereas packets containing PCRs are fed to the PCR replacement section
87
. The PCR replacement section
87
replaces the PCR contained in each packet which has been read from the buffer
89
with the post-PLL PCR
94
outputted from the PLL circuit
84
, and feeds the packets thus processed to the output section
88
. A NULL packet generation section
86
generates NULL packets in accordance with a control signal
96
outputted from the packet reading section
85
.
The output section
88
outputs the packets which have been read from the buffer
89
(including those which have been processed through the PCR replacement section
87
) and the NULL packets generated by the NULL packet generation section
86
to outside of the apparatus, as an output stream
97
.
The reason why the apparatus shown in
FIG. 13
comprises the NULL packet generation section
86
is in order to guarantee continuity of the output stream
97
. For example, if an abnormality occurs in the input stream
91
, packets in the buffer
89
may be depleted, thereby rendering the output stream
97
discontinuous. Even if packets are thus depleted, the apparatus shown in
FIG. 13
can generate NULL packets as necessary, which are then outputted as the output stream
97
. As a result, continuity of the output stream
97
is guaranteed.
However, the above-described conventional stream conversion apparatus has the following problems. Firstly, the conventional stream conversion apparatus performs PCR replacement by employing a PLL circuit and a PCR replacement section. Therefore, a PLL circuit is indispensable to the conventional stream conversion apparatus. Moreover, the operation of such a PLL circuit may become unstable depending on the PCR extraction timing in the PCR extraction section, e.g., when the PCRs contained in packets become discontinuous. Once the operation of the PLL circuit becomes unstable, the PCR replacement may become erroneous, thereby hindering the proper output of the output stream. Furthermore, in the case where a plurality of sequences of PCRs are contained in the input stream, PCR replacement may not be properly performed.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide an apparatus and method for stream conversion which solves the aforementioned problems associated with conventional stream conversion apparatuses.
The present invention has the following features to attain the object mentioned above.
A first aspect of the present invention is directed to a digital stream conversion apparatus for outputting a digital stream having a packetized format at a rate which is slower than an input rate, comprising: a time stamp assignment section for assigning, as a time stamp for each packet in an inputted digital stream comprising a plurality of packets, an input time of the packet; a packet reduction section for deleting deletable packets from the inputted digital stream and outputting remaining packets, wherein the deletable packets are packets which appear in the digital stream with a predetermined repetition pattern; a time stamp replacement section for, based on a proportion of the deletable packets in the digital stream, replacing the time stamps assigned to the packets outputted from the packet reduction section; and a packet output section for outputting the packets outputted from the time stamp replacement section, such that each packet is outputted at a time indicated by the time stamp assigned to the packet. Thus, without employing any circuit such as a PLL circuit, precise stream conversion processes can be performed in a stable manner. By incorporating such a stream conversion apparatus between a main bus and an interface circuit of an information device or a video device, for example, it becomes possible to utilize the main bus effectively and efficiently.
Until positions of the deletable packets among the packets outputted from the time stamp assignment section are ascertained, the packet reduction section may be operable to: if a packet of the same type as the deletable packets is inputted following immediately after a packet of a different type from the type of the deletable packets, delete the packet; and if packets of the same type as the deletable packets are consecutively inputted, delete any packet in an odd-numbered position among the consecutive packets and output any packet in an even-numbered position among the consecutive packets. This prevents all of the same type of packets as the deletable packets from being indiscriminately deleted from the output stream before the positions of the deletable packets are ascertained.
Alternatively, once the positions of the deletable packets among the packets outputted from the time stamp assignment section are ascertained, the packet reduction section may be operable to delete any packets which are in the ascertained positions, and output the remaining packets in the inputted digital stream, regardless of whether the remaining packets are of the same type as the deletable packets or not. This prevents all of the same type of packets as
Gotoh Shouichi
Kita Kouichi
Yamada Mikihiko
Jeanglaude Jean Bruner
Matsushita Electric - Industrial Co., Ltd.
Wenderoth , Lind & Ponack, L.L.P.
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