Apparatus and method for developing wait states during addressin

Details Apparatus and method for developing wait states during addressin Apparatus and method for developing wait states during addressin

1990-11-13

1993-10-12

Dixon, Joseph L.

Boots, shoes, and leggings

395400, 364DIG1, 3642598, 3642599, 3642618, 3642715, G06F 1206

Patent

active

052533557

ABSTRACT:
An apparatus and method for providing wait states using address bits not used in the device address decode. The upper address bits of a computer system are not used for peripheral and memory device decoding purposes. The unused bits are driven to indicate the desired number of wait states to be developed for each selected device, while still allowing a normal decode of the devices. Wait state and ready logic is provided which allows each device address to be assigned one of several possible wait state lengths by driving the most significant bits of the address. The address decode based wait state determination is overridden for RAM operations, and followed for ROM and peripheral operations.

REFERENCES:
patent: 4503491 (1985-03-01), Lushtak et al.
patent: 4611279 (1986-09-01), Andresen et al.
patent: 4613936 (1986-09-01), Andresen
patent: 5070473 (1991-12-01), Takano et al.

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