Patent
1997-06-12
1999-08-03
Treat, William M.
395572, G06F 938
Patent
active
059336293
ABSTRACT:
A superscalar microprocessor implements a microcode instruction unit with sequence control fields appended to each microcode line. The sequence control fields indicate whether a subsequent line contains a branch instruction, whether a subsequent line is the last line in a microcode sequence, and other sequence control information. The sequence control information is accessed one cycle before the microcode line. This allows the next address to be calculated in parallel with the accessing of the microcode instruction line. By generating the next address in parallel with accessing the microcode line, the time delay from accessing one microcode line to accessing the next microcode line is reduced. The sequence control field additionally indicates how many microcode instructions are in the last line of the microcode sequence. If the last microcode line of the microcode sequence contains less instructions than the number of issue positions available, fastpath, or directly decodable instructions, can be issued with the final microcode line.
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Mahalingaiah Rupaka
Miller Paul K.
Advanced Micro Devices , Inc.
Kivlin B. Noel
Merkel Lawrence J.
Treat William M.
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