Apparatus and method for detecting and handling memory-mapped I/

Details Apparatus and method for detecting and handling memory-mapped I/ Apparatus and method for detecting and handling memory-mapped I/

1987-01-22

1989-01-31

Shaw, Gareth D.

Boots, shoes, and leggings

G06F 300

Patent

active

048020850

ABSTRACT:
A method for detecting and handling memory-mapped I/O in a pipelined data processing system is provided. The method uses two signals on the system interface: when the system generates a read bus cycle, it activates an output signal if certain I/O requirements are not satisfied; an input signal is activated when the reference is to a peripheral device that exhibits certain characteristics; when the system detects that both the input signal and the output signal are active, it discards the data read during the bus cycle, serializes instruction execution and regenerates the read bus cycle, this time satisfying the requirements for I/O such that the output signal is driven inactive.

REFERENCES:
patent: 4305124 (1981-12-01), Marro et al.
patent: 4365311 (1982-12-01), Fukunaga et al.
patent: 4371927 (1983-02-01), Wilhite et al.
patent: 4498136 (1985-02-01), Sproul, III
patent: 4547848 (1985-10-01), Nishida et al.
patent: 4580238 (1986-04-01), Sawada

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