Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
2000-07-11
2003-12-02
Mai, Tan V. (Department: 2124)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
Reexamination Certificate
active
06658445
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an apparatus and method for demodulating a square root of the sum of two squares, especially to an apparatus and method for demodulating a square root of the sum of two squares using the characteristic of a binary number to reduce the hardware cost and time consumption.
2. Description of Related Art
In the field of signal processing, to demodulate a square root {square root over (I
2
+Q
2
)} of the sum of two squares of inputs I and Q is a common question. If we want to achieve an exact result of the square root, a lot of hardware cost and time will be wasted. Therefore, the researchers in the industry try to find out an approximation with an acceptable distortion to reduce the hardware cost and time consumption. A prior art is disclosed in the specification of a U.S. Patent whose application Ser. No. is 09,049,605, now U.S. Pat. No. 6,070,181, and whose title is “METHOD AND CIRCUIT FOR ENVELOPE DETECTION USING A PEEL CONE APPROXIMATION.” The prior art approximates the square root {square root over (I
2
+Q
2
)} with the value of an equation aX+bY, wherein X=|I|, Y=|Q|. The prior art firstly adopt a section-division method to divide a rectangular coordinate between 0 degree to 45 degree into a plurality of regions, and then uses a ROM to store coefficients a and b corresponding to the plurality regions. The ratio of X to Y is used to determine in which region the square root {square root over (I
2
+Q
2
)} is located, and therefore uses a look-up table to capture the coefficients a and b corresponding to the located region. Finally, a multiplier/adder is used to calculate the result of the equation aX+bY to approximate the square root {square root over (I
2
+Q
2
)}. When computing the square-root approximation, the prior art uses a ROM and a multiplier/adder, and therefore creates the drawbacks of large hardware cost and time consumption.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to resolve the drawbacks of large hardware cost and time consumption in the prior art. In order to accomplish the object, the present invention proposes an apparatus and method for demodulating a square root of the sum of two squares. Like the prior art, the present invention approximates the square root {square root over (I
2
+Q
2
)} of the sum of two squares of inputs I and Q with an equation aX+bY, wherein X=|I|, Y=|Q|. One of differences from the prior art is that the present invention proposes special coefficients a and b, which is suitable to compute the result of the equation {square root over (I
2
+Q
2
)} rapidly with a special shifting characteristic of a binary number, and therefore eliminate the disadvantages of large hardware cost and time consumption due to the use of multipliers. Besides, the present invention creates a plurality of possible approximations simultaneously, and uses a comparator to select the maximal one among the possible approximations. The maximal one is the exact approximation of the square root {square root over (I
2
+Q
2
)} of the sum of two squares of inputs I and Q. Depending on the characteristic, the present invention can eliminate the disadvantages of the prior art which uses a ROM to store a plurality of parameters.
The apparatus of the present invention mainly comprises an absolute value determining circuit, a maximal/minimal value determining circuit, a shifter/adder and a comparator. The absolute value determining circuit is used to obtain positive values of two inputs. The maximal/minimal value determining circuit is used to determine a maximal and minimal values of the positive values. The shifter/adder connected to the maximal/minimal value determining circuit is used to divide the ratio of A to B into k divisions, and the coefficients of every division are represented as a fraction whose denominator is a power of two, wherein k is a positive integer. By the characteristic that left shifting of a binary number represents multiplying the binary number by a power of two and that right shifting of a binary number represents dividing the binary number by a power of two, the values of the equation âA+{circumflex over (b)}B of the first to the
k
2
-
th
divisions are computed. The comparator is used to generate the maximal value of the
k
2
outputs of the shifter/adder, and the largest value is the approximation of the square root of the sum of two squares.
The method of the present invention mainly comprises step (a) to step (d). In step (a), an equation âX+{circumflex over (b)}Y is used to approximate a square root {square root over (I
2
+Q
2
)} of the sum of two squares of inputs I and Q, wherein X=|I| and Y=|Q|. In step (b), the ratio of X to Y is divided into k divisions, and the values of â and {circumflex over (b)} of every division are represented as a fraction whose denominator is a power of two, wherein k is a positive value. In step (c), by the characteristic that left shifting of a binary number represents multiplying the binary number by a power of two and that the characteristic of right shifting of a binary number represents dividing the binary number by a power of two, the values of the equation âA +{circumflex over (b)}B of the first to the
k
2
-
th
divisions are computed, wherein A is the maximal value of X and Y, and B is the minimal value of X and Y. In step (d), the maximal value of the equation âA+{circumflex over (b)}B of the k divisions is generated, and the maximal value is the approximation of the square root of the sum of two squares.
The present invention also can be implemented by software. Because the present invention has the advantages of simple structure and less operations, the implementation by software also has the advantages.
REFERENCES:
patent: 3829671 (1974-08-01), Gathright et al.
patent: 4553260 (1985-11-01), Belt et al.
patent: 4599701 (1986-07-01), Vojir et al.
patent: 4694417 (1987-09-01), Cantwell
patent: 4736334 (1988-04-01), Mehrgardt
patent: 4747067 (1988-05-01), Jagodnik, Jr. et al.
patent: 5459683 (1995-10-01), Uesugi et al.
patent: 5603112 (1997-02-01), Gabato et al.
patent: 5862068 (1999-01-01), Onodera
patent: 6070181 (2000-05-01), Yeh
Gau Yow-Ling
Meng Ching-Chun
Wang Bor-Chin
Burns Doane Swecker & Mathis L.L.P.
Chun-Shan Institute of Science and Technology
Mai Tan V.
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