Apparatus and method for defect testing of integrated circuits

Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

3241581, G01R 3126

Patent

active

060313862

ABSTRACT:
An apparatus and method for defect and failure-mechanism testing of integrated circuits (ICs) is disclosed. The apparatus provides an operating voltage, V.sub.DD, to an IC under test and measures a transient voltage component, V.sub.DDT, signal that is produced in response to switching transients that occur as test vectors are provided as inputs to the IC. The amplitude or time delay of the V.sub.DDT signal can be used to distinguish between defective and defect-free (i.e. known good) ICs. The V.sub.DDT signal is measured with a transient digitizer, a digital oscilloscope, or with an IC tester that is also used to input the test vectors to the IC. The present invention has applications for IC process development, for the testing of ICs during manufacture, and for qualifying ICs for reliability.

REFERENCES:
patent: 4646299 (1987-02-01), Schinabeck et al.
patent: 4710704 (1987-12-01), Ando
patent: 5392293 (1995-02-01), Hsue
patent: 5430305 (1995-07-01), Cole, Jr.
patent: 5519333 (1996-05-01), Righter
patent: 5523694 (1996-06-01), Cole, Jr.
patent: 5731700 (1998-03-01), McDonald
patent: 5917331 (1999-06-01), Persons
J. M. Soden, C. F. Hawkins, R. K. Gulati, and W. Mao, "I.sub.DDQ Testing: A Review," Journal of Electronic Testing, vol. 3, pp. 291-303, 1992. (No Month Available).
K. M. Wallquist, A. W. Righter, and C. F. Hawkins, "A General Purpose I.sub.DDQ Measurement Circuit," Proceedings of the IEEE International Test Conference 1993, paper No. 31.3, pp. 642-651, 1993. (No Month Available).
K. M. Wallquist, "On the Effect of I.sub.SSQ Testing in Reducing Early Failure Rate," Proceedings of the IEEE International Test Conference 1995, paper No. 38.3, pp. 910-915. (No Month Available).
K. Isawa and Y. Hashimoto, "High-Speed I.sub.DDQ Measurement Circuit," Proceedings of the IEEE International Test Conference 1996, paper No. 5.2, pp. 112-117, 1996. (No Month Available).
A. W. Righter, J. M. Soden, and R. W. Beegle, "High Resolution I.sub.DDQ Characterization and Testing--Practical Issues," Proceedings of the IEEE International Test Conference 1996, paper No. 9.3, pp. 259-268, 1996. (No Month Available).
J. F. Plusquellic, D. M. Chiarulli, and S. P. Levitan, "Digital Integrated Circuit Testing using Transient Signal Analysis," Proceedings of the IEEE International Test Conference 1996, paper No. 18.1, pp. 481-490, 1996. (No Month Available).
T. W. Williams, R. H. Dennard, R. Kapur, M. R. Mercer, and W. Maly, "Iddq Test: Sensitivity Analysis of Scaling," Proceedings of the IEEE International Test Conference 1996, paper No. 29.3, pp. 786-792, 1996. (No Month Available).
J. M. Soden and R. E. Anderson, "IC Failure Analysis: Techniques and Tools for Quality and Reliability Improvement," Proceedings of the IEEE, vol. 81, pp. 703-715, May 1993.
J. S. Beasley, H. Ramamurthy, J. Ramirez-Angulo, and M. DeYong, "I.sub.DD Pulse Response Testing of Analog and Digital CMOS Circuits," Proceedings of the IEEE International Test Conference 1993, paper No. 31-1, pp. 626-634, 1993. (No Month Available).
V. Stapjakova, J. Vutas, and H. Manhaeve, "Detecting CMOS Failures Applying Transient Power Supply Current Monitoring," Proceedings of the European Test Workshop, 1997. (No Month Available).

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Apparatus and method for defect testing of integrated circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Apparatus and method for defect testing of integrated circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus and method for defect testing of integrated circuits will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-686376

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.