Pulse or digital communications – Bandwidth reduction or expansion – Television or motion video signal
Reexamination Certificate
1996-08-20
2001-08-28
Kelley, Chris (Department: 2613)
Pulse or digital communications
Bandwidth reduction or expansion
Television or motion video signal
Reexamination Certificate
active
06282244
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to the decoding of compressed digital data, and more particularly, to an apparatus and method for decoding compressed digital video data that has been compressed, for example, in a format compliant with the MPEG (Motion Picture Experts Group I) standard or the JPEG (Joint Picture Experts Group) standard.
2. Description of the Related Art
Compact discs are high capacity data storage means that are widely used to supply multimedia applications including audios and videos. When converted into digital form, videos usually result in quite an enormous amount of bits and bytes, thus requiring quite a large space to store. To cope with this problem, a variety of compression methods are available for compressing the digital video data before actually storing them on compact discs. When in use, the compressed data has to be decoded (decompressed) before it can be actually processed for practical applications. The decoding process has to be fast for interactive applications. Current video decoding methods are fast, but are still not fast enough for real interactive applications.
FIG.
1
through
FIG. 3
are block diagrams depicting a conventional apparatus for decoding compressed, for example, digital video data that has been compressed in a format specifically in compliance with the MPEG (Motion Picture Experts Group I) standard or the JPEG (Joint Picture Experts Group) standard. As shown in
FIG. 1
, the conventional apparatus comprises a variable length decoding (VLD) circuit
10
, a zig-zag buffer
20
, an inverse quantizer
30
, and an inverse discrete cosine transfer (IDCT) circuit
40
.
The VLD circuit
10
receives a bit stream of compressed digital video data via an input data line
11
and then compares the compressed digital video data with values prestored in a parameter table
13
so as to generate a first bit sequence of a fixed length which is sent via the data line
21
to the zig-zag buffer
20
.
The zig-zag buffer
20
receives the first bit sequence from the data line
21
and stores the first bit sequence in a zig-zag manner, so as to generate a second bit sequence which is sent via the data line
31
to the inverse quantizer
30
.
The inverse quantizer
30
receives the second bit sequence from the data line
31
and converts the second bit sequence by a conventional inverse quantization method into a frequency-division binary signal which is sent via the data line
41
to the IDCT circuit
40
.
The IDCT circuit
40
receives the frequency-division binary signal from the data line
41
and converts the frequency-division binary signal by an inverse discrete cosine transfer function into a time-division binary signal representative of the decoded data. This completes the process of decoding of the compressed data.
Referring further to
FIG. 2
, there is shown a block diagram of the circuit structure of the zig-zag buffer
20
, which includes a write-in address generator
26
, a multi-port random accesss memory (RAM) unit
27
, and a read-out address generator
28
. When the first bit sequence from the VLD circuit
10
is received by the zig-zag buffer
20
, the write-in address generator
26
generates a read-in address signal and sends it via the address bus
22
to the RAM
27
so as to store the received data in corresponding addresses in the RAM
27
. The read-in address signal is devised in such a way that the received data is stored in a predetermined zig-zag manner in the RAM
27
. After that, the read-out address generator
28
generates a read-out address signal and sends it via the address bus
23
to the RAM
27
so as to fetch data in corresponding addresses. The data thus fetched from the RAM
27
is output via the data line
31
and will be referred to as the second bit sequence hereinafter.
Referring further to
FIG. 3
, there is shown a block diagram of the IDCT circuit
40
which includes a serial-to-parallel converter
45
and an IDCT core unit
46
. When the frequency-division binary signal from the inverse quantizer
30
is received by the IDCT circuit
40
via the data line
41
, the received data is converted from serial to parallel and then sent via the data bus
42
to the IDCT core unit
46
. The parallel data is then processed by the IDCT core unit
46
according to an inverse discrete cosine transfer function into a plurality of time-division binary signal bits which, after being converted to serial form, represent a bit stream of the decoded data and is output via the data line
51
.
In the above described conventional apparatus, the compressed digital video data on the data line
11
and the first bit sequence on the data line
21
are in compressed form, whereas the second bit sequence on the data line
31
, the frequency-division binary signal on the data line
41
, and the time-division binary signal on the data line
51
are in a decoded form and are transmitted at pixel rates. Since compressed data is significantly less in volume than the original data, for example, with a compression ratio typically at 1:10 by the MPEG I standard, a processing lag will occur between the input end and the output end of the conventional apparatus of FIG.
1
. In the zig-zag buffer
20
, since the write-in address generator
26
and the read-out address generator
28
perform the data read-out operation in a serial manner so that the data has to be converted by the serial-to-parallel converter
45
into parallel form before being sent to the IDCT core unit
46
, the data flow there is somewhat slower than the IDCT core unit
46
can handle. Thus, the serial read-out operation in the zig-zag buffer
20
, and the need for the serial-to-parallel converter
45
to convert the serial binary signal into parallel form, cause a delay in the decoding process. This delay affects significantly the performance of the process of decoding the compressed video data. There exists therefore a need for a new decoding apparatus and method which can enhance the performance of the decoding process by eliminating the serial-to-parallel conversion performed in the conventional apparatus.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide an apparatus and method for decoding compressed digital video signals, which can enhance the performance of the decoding process by eliminating the serial-to-parallel conversion performed in the conventional apparatus.
In accordance with the foregoing and other objects of the invention, a new and improved apparatus and method for decoding compressed digital video signals are provided. The apparatus includes a VLD circuit for generating a first bit sequence of a fixed length by decoding the received compressed digital video data. An inverse quantizer is subsequently used to convert the first bit sequence by an inverse quantization method, into a second bit sequence. A zig-zag buffer is then used to store the received second bit sequence in specific locations and output a plurality of frequency-division binary signal bits concurrently in parallel. Finally, an IDCT circuit is used to process the plurality of frequency-division binary signal bits by an inverse discrete cosine transfer function to accordingly generate a plurality of time-division binary signal bits which are combined into a time-division serial binary signal representative of decoded data for the compressed digital video data.
The method according to the invention includes generating a first bit sequence of a fixed length by decoding the compressed digital video data. The first bit sequence is converted by an inverse quantization procedure into a second bit sequence. The second bit sequence is then stored in a specific format. Accordingly, a plurality of frequency-division binary signal bits are output concurrently in parallel. The output frequency-division binary signal bits are processed according to an inverse discrete cosine transfer function so as to generate a plurality of time-division binary signal bits. These signal bits are combined into a time-division serial binary
Kelley Chris
Philippe Grims
Rabin & Berdo P.C.
United Microelectronics Corp.
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