Apparatus and method for decoding and trace back of...

Pulse or digital communications – Receivers – Particular pulse demodulator or detector

Reexamination Certificate

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Reexamination Certificate

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07031407

ABSTRACT:
A system for generating and storing trace bits for Viterbi decoding of binary convolution codes includes at least one arithmetic logic unit (ALU) for determining the trace bits, and a first register and a second register for storing the trace bits. The first register stores a first half of a series of trace bits for N states in sequential order and the second register stores a second half of the series in sequential order. A binary convolution decoder having multiple stages each having N states includes at least one arithmetic logic unit (ALU), a first register and a second register, and a storage device. The at least one ALU determines trace bits for each of the N states for each of the multiple stages. The first and second registers store trace bits of at least a portion of one stage. The storage device has memory cells. For each of the multiple stages, a group of at least one memory cell stores the N trace bits in sequential order. The system also includes means for tracing back, stage by stage, through the memory cells using the trace bits. Each of the memory cells has a length of at least N bits and the means for tracing back is operative to trace back in as few as two cycles per stage.

REFERENCES:
patent: 5715470 (1998-02-01), Asano et al.
patent: 5802115 (1998-09-01), Meyer
patent: 5987490 (1999-11-01), Alidina et al.
patent: 6029267 (2000-02-01), Simanapalli et al.
patent: 6084925 (2000-07-01), Baek
patent: 2002/0010895 (2002-01-01), Mujtaba
Lou, H.L., “Implementing the Viterbi Algorithm”, IEEE Signal Processing Magazine, Sep. 1995, pp. 42-52.
Texas Instruments TMS320C54X User's Guide, (3 / 15-17; 8 / 46-52; 8/ 64; and 12/ 47-50).

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