Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
1999-10-29
2003-01-28
Malzahn, David H. (Department: 2124)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
Reexamination Certificate
active
06513055
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
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STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
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BACKGROUND OF THE INVENTION
The present invention relates to automotive electronics and in particular a method and apparatus for efficiently transmitting digital signals in an automotive environment.
Present day automobiles must process and transmit multi-bit digital data. Such data may be transmitted on multiple conductors, where each conductor carries one bit of the multi digital word (“in parallel”), or on as few as two conductors where the conductors carry each bit of the digital word in sequence (“serially”) according to techniques well known in the art. Generally, the transmission of digital data for any significant distance in the automobile is done serially to reduce wiring cost and weight. However, within processing circuitry receiving or transmitting the digital data, such as microprocessors, a parallel bus structure is normally used.
The number of bits in the transmitted digital words, their “width”, is preferably minimized to reduce the cost and complexity of the integrated circuits needed to process the data and to reduce the bandwidth needed to transmit the data on the serial conductor. The serial conductors may be shared with other systems or be limited in bandwidth for reasons of power consumption or noise immunity.
One method of reducing the data width of an automotive signal is to truncate the digital word representing that signal by removing the least or most significant bits of the digital word. For example, a ten-bit data value from an accelerometer used to trigger a passive restraint system such as an air bag, and representing 128 g's range may be truncated to eight-bits by eliminating the two least significant bits. This truncation reduces the resolution of the signal from 0.125 g's to 0.5 g's. Alternatively, the ten-bit data value may be truncated to eight-bits by eliminating the two most significant bits causing a reduction in range from 128 g's to 32 g's.
Normally the necessary range is fixed as a function of the application. In the example of the accelerometer, the fill range of 128 g's is required for activation of the airbags. On the other hand, a reduction in resolution may also be unacceptable because it will produce too great of an accumulated error. Generally, a decrease in resolution increases the “quantization error” of the samples, the quantization error being a downward bias caused by implicit rounding during the truncation process. Any time multiple samples are combined, this bias is multiplied producing an accumulated error. If resolution is decreased, an unacceptably large accumulated. error can result. In the example of the accelerometer, during periodic calibration of the zero value of the accelerometer, a number of samples of the accelerometer's output are combined to determine an acceleration offset for the particular accelerometer. Decreasing the resolution of the accelerometer signal causes the accumulated error in the calibration value to quickly rise to unacceptable values.
Ideally there would be a way to minimize the data width of automotive signals without reducing the range of the signal and without producing large accumulated errors over time.
BRIEF SUMMARY OF THE INVENTION
The present inventor has recognized that the accumulated error resulting from a truncation of the least significant bits of a data word, can be substantially decreased if the truncated bits are saved until their total has risen beyond the threshold of the truncation. When this occurs, the next truncated word can be incremented to effectively eliminate the accumulated error caused by the truncation up to that point. By using this process, an integration or summing of the truncated data words will show a much lower error over time.
Specifically then, the present invention provides a method or an apparatus for performing the method of receiving a digital word having a first number of bits including lower order bits. The lower order bits are truncated from the digital word to produce a truncated digital word having a second number of bits less than the first number of bits. An accumulator stores a running total of the truncated lower order bits of the digital word. At times when the value stored in the accumulator exceeds a predetermined threshold, the threshold is subtracted from the accumulator and the truncated word and the threshold value are transmitted. When the accumulator value does not exceed the predetermined threshold, the truncated word is transmitted without the threshold value.
Thus, it is one object of the invention to reduce the width of transmitted digital data, and thus the cost and burden of the transmission, without causing excessive accumulated error. Increased quantization error inherent in truncating lower ordered bits is compensated for by periodically incrementing the values of transmitted data words when excess accumulated error has collected.
The predetermined threshold may equal the place value of the least significant bit of the truncated digital word. The truncated word and threshold may be added together prior to transmission.
Thus, it is another object of the invention to provide a method of correcting the accumulated error without the need for a separate data transmission for the correction value alone. By accumulating the truncated bits until their sum equals the value of the least significant bit of the truncated word, the truncated word that is already slated for transmission is simply incremented by the threshold value.,
The method may include the steps of repeating the transmission of digital words and integrating the received truncated transmissions as modified by the periodic addition of the threshold value.
Thus, it is another object of the invention to provide a system that minimizes accumulated error in signal processing which includes a step of integration.
The invention may include the additional steps of producing a plurality of average values of the digital words and truncating those average values to produce truncated average values of equal width with the truncated digital words. The bits truncated from the average value are then subtracted from the accumulator value and the truncated average values are subtracted from the truncated digital words to produce a transmission value. When the accumulator value is above the threshold, the threshold is added to the transmission value whereas when the accumulator value is below the predetermined threshold, the transmission value is transmitted alone.
Thus, it is another object of the invention to provide,for a zero correction of a digitized signal that is also resistant to the buildup of accumulated error caused by quantization.
The average values may average the truncated digital words.
Thus, it is another object of the invention to simplify the circuitry necessary to compute the average value by allowing it to operate on the truncated digital words.
The foregoing and other objects and advantages of the invention will appear from the following description. In the description, reference is made to the accompanying drawings which form a part hereof and in which there is shown by way of illustration a preferred embodiment of the invention. Such embodiment does not necessary represent the full scope of the invention, however, and reference must be made to the claims herein for interpreting the scope of the invention.
REFERENCES:
patent: 4236224 (1980-11-01), Chang
patent: 4727506 (1988-02-01), Fling
patent: 5218563 (1993-06-01), Juri et al.
patent: 5329475 (1994-07-01), Juri et al.
patent: 5463570 (1995-10-01), Nakata
patent: 5493343 (1996-02-01), Knutson et al.
patent: 5696601 (1997-12-01), Metcalfe et al.
Malzahn David H.
Quarles & Brady LLP
Visteon Global Technologies Inc.
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