Apparatus and method for data induced condition signalling

Details Apparatus and method for data induced condition signalling Apparatus and method for data induced condition signalling

1993-01-15

1994-01-11

Beausoliel, Jr., Robert W.

Excavating

371 291, 371 165, G06F 1100

Patent

active

052788407

ABSTRACT:
In a data processing system, an instruction is disclosed that generates a fault when a predetermined register position (e.g., the low or least significant bit position) has a predetermined logic signal (e.g., a logic `0` signal). This instruction provides a mechanism to determine when a Boolean value indicates a presence of a fault condition and provides a mechanism to generate the fault when present. For example, in arrays of memory locations that can be addressed by a program, this instruction can respond to the presence of an array address (or reference) that is outside the prescribed bounds of the array. When an invalid address is identified, a signal is entered in the low (i.e., least significant) bit position of a processor scalar register. The instruction repertoire includes a Fault on Low Bit Clear instruction that tests the contents of the scalar register low bit position, and when a logic `0` signal is found therein, an exception signal is generated and applied to the control program of the data processing system.

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