Excavating
Patent
1989-06-30
1990-06-26
Fleming, Michael R.
Excavating
371 291, 371 165, G06F 1132
Patent
active
049378244
ABSTRACT:
In a data processing system, an instruction is disclosed that generates a fault when a predetermined register position (e.g, the low or least significant bit position) has a predetermined logic signal (e.g., a logic `0` signal). This instruction provides a mechanism to determine when a Boolean value indicates a presence of a fault condition and provides a mechanism to generate the fault when present. For example, in arrays of memory locations that can be addressed by a program, this instruction can respond to the presence of an array address (or reference) that is outside the prescribed bounds of the array. When an invalid address is identified, a signal is entered in the low (i.e., least significant) bit position of a processor scalar register. The instruction repertoire includes a Fault on Low Bit Clear instruction that tests the contents of the scalar register low bit position, and when a logic `0` signal is found therein, an exception signal is generated and applied to the control program of the data processing system.
REFERENCES:
patent: 4079453 (1978-03-01), Dahl
patent: 4084230 (1978-04-01), Matick
patent: 4100605 (1978-07-01), Holman
patent: 4145738 (1979-03-01), Inoue et al.
patent: 4167781 (1979-09-01), Beccia et al.
patent: 4228496 (1980-10-01), Katzman et al.
patent: 4320466 (1982-03-01), Myers
patent: 4438512 (1984-03-01), Hartung et al.
patent: 4451885 (1984-05-01), Gerson et al.
patent: 4592053 (1986-05-01), Matsuura
patent: 4593391 (1986-06-01), Mizushima
patent: 4679195 (1987-07-01), Dewey
patent: 4685053 (1987-08-01), Hattori
patent: 4745602 (1988-05-01), Morrell
Radin, "The 801 Minicomputer", SIGARCH, vol. 10, No. 2, (1982), pp. 39-47.
Lutter, "Shift Register Verifier", IBM Technical Disclosure Bulletin, vol. 19, No. 12, (1977).
Auslander, et al. "An Overview of the PL.8 Compiler", ACM SIGPLAN Notices, vol. 17, No. 6, (1982), pp. 22-31.
Nelson, "Check Array Boundaries," 386, (1988), p. 15.
"Applications Instruction Set," The Intel 80386 Programmer's Reference Manual, (1987), pp. 3-24, 3-25.
"80386 Instruction Set," The Intel 80386 Programmer's Reference Manual, (1987), pp. 17-26, 17-27.
Bhandarkar Dileep
Cardoza Wayne
Cutler David N.
Orbits David A.
Witek Richard T.
Digital Equipment Corporation
Fleming Michael R.
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