Apparatus and method for data error detection and correction and

Details Apparatus and method for data error detection and correction and Apparatus and method for data error detection and correction and

1990-12-27

1993-07-06

Atkinson, Charles E.

Excavating

371 511, G06F 1110

Patent

active

052260437

ABSTRACT:
An error detection and correction apparatus and method in a memory system for performing single symbol error correction and at least double symbol error detection of data errors and single symbol error detection and at least double symbol error detection of addressing errors using a modified Reed Solomon code. A first of three parity symbols in a codeword is used to determine the value of a single symbol error, if any, over a memory word comprising data symbols and its corresponding address comprising address symbols. A second parity symbol is used to locate a single symbol error, and a third parity symbol is used to detect at least two errors in the data and address symbols. The three parity symbols are used to generate syndromes which determine if there is an error and what corrective action to take. In calculating product terms for the modified Reed Solomon code, a technique of bit padding that requires no additional memory is used to match the number of bits needed in the Reed Solomon code data symbols to the bit width of a memory chip of a memory array in the memory system.

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