Electrical pulse counters – pulse dividers – or shift registers: c – Systems – Identifying or correcting improper counter operation
Reexamination Certificate
1999-11-04
2001-04-10
Wambach, Margaret R. (Department: 2816)
Electrical pulse counters, pulse dividers, or shift registers: c
Systems
Identifying or correcting improper counter operation
C377S045000, C327S379000
Reexamination Certificate
active
06215838
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an apparatus and method for eliminating noise, and more particularly to an apparatus and method for cumulatively eliminating the superimposition of extra-signal fluctuations that corrupt an information signal. Still more particularly, the present invention relates to an apparatus and method for recovering an information signal corrupted by noise.
2. Description of the Prior Art
Noise commonly exists in a communication system to adversely affect the communication of a clean information signal. While the information signal is corrupted to some extent by the superimposition of the noise during the transmission, the voltage potential of the received information signal becomes unpredictable.
For instance, most of the modern telephone companies provide a call-waiting service through which a third party can be selectively connected to a called party. This is usually accomplished by firstly sending a composite signal (for example, a combined 2130 Hz and 2750 Hz signal) from a central exchange office to the called party. Subsequently, a detecting circuit located near the called party is used to detect this composite signal, and then respond to the central exchange office. Moreover, the central exchange office may further provide pertinent information of the third party to the called party.
Unfortunately, during the active period (for example, about 80 ms) of the composite signal, the detecting circuit may miss the composite signal due to the fact that the composite signal is probably corrupted by the surrounding sound signal. Moreover, the detecting circuit may mis-detect a normal sound signal as the composite signal, thereby false triggering a composite signal.
An apparatus in the art as shown in
FIG. 1
was disclosed to overcome the aforementioned problem. A counter
11
is used to detect an incoming signal IDET by continuously counting under a system clock CK. The counter
11
is reset by a reset circuit
12
whenever absence of the input signal IDET exists, for example, at time t1, t2 or t4 as shown in FIG.
2
A. Further, the count of the counter
11
is fed to a determining circuit
13
, which outputs an active signal DET
1
whenever the count reaches a threshold value TH, for example, at time t3.
Unfortunately, the conventional apparatus of
FIG. 1
can not be used to detect a severely corrupted signal such as that shown in FIG.
2
B. As demonstrated in
FIG. 2B
, the count of the counter
11
is repeatedly reset whenever encountering the noise (which has low voltage potential in this example), thereby missing the input signal IDET. The disadvantage of the conventional apparatus of
FIG. 1
can not be improved even by using a lower threshold value TH, which will undesirably result in false triggers.
For the foregoing reasons, there is a need for an apparatus and method for eliminating the superimposition of extra-signal fluctuations that corrupt an information signal, and overcoming the disadvantages of the prior apparatus or method that usually misses detecting the input signal or generates false triggering in detecting a severely corrupted signal.
SUMMARY OF THE INVENTION
In accordance with the present invention, an apparatus and method is provided for cumulatively eliminating the superimposition of extra-signal fluctuations that corrupt an information signal. The present invention eliminates the disadvantages of the prior apparatus or method that usually misses detecting the input signal or generates false triggering in detecting a severely corrupted signal.
In one embodiment, an up-down counter is used to count up when an incoming signal is active, and count down when the signal is not active. A determining circuit, which asserts an output signal when the counter reaches a predetermined up-threshold value, is also included. The output signal remains asserted until the counter reaches a predetermined down-threshold value, wherein the up-threshold value is generally greater than the down-threshold value. Finally, a limit controller is used to prevent the counter from counting beyond a predetermined first limit value, and from counting below a predetermined second limit value, wherein the second limit value is generally equal to or less than the down-threshold value. In the embodiment, a resetting circuit is further included to respond to the output signal, so that the counter is reset when the counter counts down reaching the down-threshold value; and a setting circuit is further included for setting the counter to the first limit value when the output signal is asserted.
REFERENCES:
patent: 4667338 (1987-05-01), Toyonaga et al.
Hwang Jyn-Guo
Ku Chiung-Ching
Liu Yen-Yi
Tarng Strung-An
Bacon & Thomas PLLC
Elan Microelectronics Corp.
Wambach Margaret R.
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