Apparatus and method for CRC computation over fixed length block

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371 401, G06F 1110

Patent

active

054105463

ABSTRACT:
The present invention discloses a method and apparatus for computing CRC codes for fixed length page buffers of user data where the user data arrives from a transmission device in variable length packets with the packet contents being out of sequential order. The received data is written to a storage device after being restored to the correct sequential order. The data packets are comprised of a header portion and a data portion. The transmission and compression methods commonly employed by the transmission device dictates that the header portion of each packet follows the data portion. The present invention computes a complete CRC code for the data stored in a page buffer in real time as the packets are received by using several registers for saving intermediate CRC codes and circuitry to combine partial CRC codes for those packet portions received out of order. Additional circuitry is provided which reorders the data packet portions received out of order back into sequential order as the data is stored in a page buffer memory in real time. Computing the CRC codes in real time permits the saving of costs associated with other approaches that significantly buffer the incoming packets to permit subsequent reordering and CRC computation. The present invention assures data integrity of data from the time it is received from the compression unit until the time it is sent to the storage device. In addition, the present inventions ability to compute the CRC codes real time maintains optimal performance of data throughput of the storage subsystem. The present invention alleviates problems relating to delaying new data packet transmissions as deferred CRC computations are performed on previous packets reordered in temporary buffer memory.

REFERENCES:
patent: 4667326 (1987-05-01), Young et al.
patent: 5274772 (1993-12-01), Dunn et al.

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