Electricity: conductors and insulators – Boxes and housings – Hermetic sealed envelope type
Reexamination Certificate
2001-08-31
2003-11-18
Ngo, Hung V. (Department: 2831)
Electricity: conductors and insulators
Boxes and housings
Hermetic sealed envelope type
C257S680000, C257S738000, C257S787000
Reexamination Certificate
active
06649832
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of electronic packaging. Specifically, the invention is an apparatus and method for coupling with an internally packaged component and/or connection on the die and/or substrate of a surface mount package.
2. Related Art
As electronic systems miniaturize and system operating frequencies rise, connection lengths and packaging become important aspects of full system performance. Short connection lengths and compact packaging are advantageous. Electrical design facilitating high performance at high frequencies is crucial. Interfaces effectuating data transfer at high frequencies without signal degradation, optical transceivers and other devices enabling signal exchange between electronic and optical media, and testing access enabling performance evaluation and system debugging are all desirable.
Modern electronic packaging of integrated circuits (IC) and other semiconductor devices is trending toward higher densities on more compact packages with higher numbers of external connections, commonly surface mounted on and connected to a printed circuit boards (PCB). One such surface mount package is the common lead frame package. Another, offering electrical advantages at the high frequencies becoming common, is the ball grid array (BGA).
A BGA includes a substrate onto which a pattern of conductive traces, typically covering the full surface of the substrate, and bonding pads are printed. The traces are also electrically connected to bonding pads on the bottom of the substrate. The bonding pads are masked, solder mask material is then deposited over the entire top surface, and the mask material is then removed such that the bonding pads are exposed. A hard protective layer may be deposited on the bonding pads, so as to harden their surface to facilitate wire bonding.
A die, which may be an IC or other semiconductor device, is mounted atop the substrate, and wire bonded to its upper bonding pads, electrically connecting the die to the bonding pads. The die, and all but a part of the remaining exposed top of the substrate, is covered by a molded cover. Typically, the cover compound is an organic biphenyl polymer, another plastic or other polymer, or a ceramic. The resulting structure is then trimmed, typically by cutting, at all edges of the substrate.
Conductive appurtenances, such as solder balls, are typically arrayed over the bottom surface of the substrate, electrically connected to the array of bonding pads thereon. The solder balls or other connectors are thereby connected to the IC or other semiconductor device constituting the die. Through the solder balls or other appurtenances, the IC or other semiconductor device constituting the die may be simultaneously surface mounted and electrically connected to appropriate contacts printed, typically in an array, on a PCB.
Other surface mount packages, such as the chip scale package (CSP) are becoming part of trend in electronic packaging, offering increases in electronic density and physical compactness. There are lead frame CSPs; there are also BGA chip scale packages (BGACSP), such as array molded BGA, fine pitch BGA, and micro BGA. Other relevant modern surface mount packages include the flip chip, quad FlatPack (QFP), thin QFP (TQFP), ceramic QFP (CQFP), small profile QFP (SQFP), and plastic QFP (PQFP). These surface mount packages are well known in the art.
Optical transceivers, and other opto-electronic devices enabling signal exchange between electronic and optical media are often packaged discretely, or in relatively low-scale integration packages. Typically, they have relatively few connecting pins or other connection modalities. Optically active components, such as a photodiode (PD) and a laser diode (LD), are often packaged, sometimes together, integrated with supporting electronics, such as an amplifier and a laser driver and Peltier cooler, on a ceramic substrate. A quartz, glass, or other, wavelength-appropriate window, is mounted thereto. A metallic cover is soldered on, hermetically sealing the device.
Optical transceivers are integral parts of many electronic data systems, where they receive control and data for transmission from and send feedback and data received to logic devices such as a serializer/deserializer (SERDES). Optical transceivers, typically with relatively few connecting pins, are either mounted directly upon a printed circuit board (PCB), or connected via a socket, which is itself mounted directly upon the PCB. In the conventional arrangement, pins of the optical transceiver are connected, individually, to a SERDES device or another logic chip, typically with a larger number of connections than the optical transceiver. Optical transceivers, due to the short service lives of their lasers relative to other system components or due to a change in application, such as from short to long haul transmission, may require replacement before other system components.
While effectuating data transfer at high frequencies is somewhat improved by the SMP, and optical transceivers enabling signal exchange between electronic and optical media may be used in conjunction with them, the conventional art is problematic.
Direct functional interfacing with individual constituent subcomponents of the internal die component or with particular circuit nodes or conductive trace locales of the SMP, without high frequency signal degradation and other serious electrical problems, is particularly difficult. This is one major drawback of the conventional art. Another is that testing access, directly to the internal die component of the SMP or to a particular circuit node or conductive trace locale of the SMP, enabling performance evaluation and system debugging, is all but impossible. Both direct functional interfacing and providing direct testing access with individual constituent subcomponents of the internal die component or with particular circuit nodes or conductive trace locales of the SMP, has not been fully achieved in the conventional art. Substitutes conventionally used are costly, somewhat ineffective, and applied substantially ad hoc. Further, high frequency electrical performance suffers.
Mounting and connecting optical transceivers to PCBs conventionally leaves an inordinately large footprint upon the PCB. Typically, optical transceivers are relatively large, physically. Further, the mismatch between their relatively low number of connection pins and the relatively high number of connections required by SERDES and other data transfer logics poses an electrical routing problem, leaving an even larger PCB footprint, and precluding fully functional integration with the SERDES. Sockets, used to allow changeability of the optoelectronic device, tend to degrade high frequency signals. Also, conventional optoelectronic packaging is relatively expensive.
What is needed is a method and/or apparatus that effectuates a direct functional interface directly with individual constituent subcomponents of the internal die component, or with particular circuit nodes or conductive trace locales of the surface mount package (SMP), without high frequency signal degradation or other electrical problems. What is also needed is a method and/or apparatus that effectuates testing access, directly to the internal die component of the SMP or to a particular circuit node or conductive trace locale of the SMP, enabling performance evaluation and system debugging. Further, what is needed is a method and/or apparatus that effectuates integration of SMP with an opto-electronic package. Further still, what is needed is a method and/or apparatus that achieves these advantages with minimal cost.
SUMMARY OF THE INVENTION
An embodiment of the present invention provides a method and apparatus that effectuates a direct functional interface directly with individual constituent subcomponents of the internal die component, or with particular circuit nodes or conductive trace locales of the surface mount package, without high frequency signal degradation or other el
Brophy Brenor L.
Lie James H.
Wright Andrew J.
Cypress Semiconductor Corporation
Ngo Hung V.
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