Apparatus and method for correction of error caused by...

Amplifiers – With semiconductor amplifying device – Including differential amplifier

Reexamination Certificate

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C330S263000, C330S267000

Reexamination Certificate

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11035156

ABSTRACT:
A buffer circuit is arranged for offset cancellation between an input voltage and a buffered voltage. The buffer circuit includes two bias current sources, two p-type transistors, and two n-type transistors. Further, the base-emitter voltages of the two p-type transistors and the two n-type transistors are arranged to form a translinear loop. The translinear loop is arranged to provide the buffered voltage from the input voltage. One of the bias sources is arranged to provide a bias current to one of the p-type transistors, and the other bias circuit is arranged to provide a bias current to one of the n-type transistors. One of the bias current circuits is arranged to actively sense the reverse saturation currents of the p-type transistors and the n-type transistors, and to provide its bias current so that the offset voltage between the input voltage and the buffered voltage is substantially cancelled.

REFERENCES:
patent: 5323122 (1994-06-01), Bowers
patent: 5578967 (1996-11-01), Harvey
patent: 6160451 (2000-12-01), Floru
patent: 6552613 (2003-04-01), Murray et al.

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