Apparatus and method for controlling the initiating of a synchro

Details Apparatus and method for controlling the initiating of a synchro Apparatus and method for controlling the initiating of a synchro

1995-04-04

1997-03-25

Black, Thomas G.

Boots, shoes, and leggings

364230, 364DIG2, 39518304, 39518305, 39520019, 395672, G06F 1100, G06F 9455

Patent

active

056153279

ABSTRACT:
A multiprocessor (MP) computer sytem which allows target CPU(s) to continue processing instructions while other target CPU(s) are processing instructions of emulation code to reach their end of a Domain Unit of Operation before synchronization. A two-level MP sync is used since the target CPUs must be in between units of operation when the updates occur since a unit of operation can be one instruction or it can be many instructions that together emulate one instruction. Two level MP sync allows CPUs that are going to be serialized to continue to process single instructions (no emulation code) while other target CPUs are in emulation mode.

REFERENCES:
patent: 4511961 (1985-04-01), Penton
patent: 5109522 (1992-04-01), Lent et al.
patent: 5187790 (1993-02-01), East et al.
patent: 5222229 (1993-06-01), Fukuda et al.
patent: 5353436 (1994-10-01), Horst
patent: 5361369 (1994-11-01), Kametani

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