Apparatus and method for controlling pipelined data transfer sch

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Details

395496, 395401, 395492, G06F 1202

Patent

active

056110685

ABSTRACT:
A controller for transferring data between operational stages in a computer is provided. The controller includes a shift register for receiving a scheduling word and a counter for generating an address which corresponds to a datum to be transferred. The controller can be pre-programmed with a scheduling word to effect execution overlap between the stages.

REFERENCES:
patent: 3755784 (1973-08-01), Greek, Jr. et al.
patent: 4052704 (1977-10-01), Franaszek
patent: 4513400 (1985-04-01), Masaki
patent: 4905143 (1990-02-01), Takahashi et al.
patent: 5201054 (1993-04-01), Dudhela
patent: 5530890 (1996-06-01), Moore et al.

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