Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2006-07-25
2006-07-25
Lao, Lun-yi (Department: 2629)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S204000, C345S098000, C348S537000
Reexamination Certificate
active
07081878
ABSTRACT:
An apparatus and a method for accurately controlling the phase of a sampling clock signal in an LCD system, wherein the sampling clock is generated by a phase lock loop and delayed in response to a phase delay quantity generated by a controller. The controller continuously generates a first phase delay quantity until a horizontal line width of a digital image signal is equal to a desired width, stores a first total phase delay quantity corresponding to how many times the first phase delay quantity was generated, continuously generates a second phase delay quantity until the current horizontal line width is greater than the desired width, stores a second total phase delay quantity corresponding to how many times the second phase delay quantity was generated, and controls the phase delay of the sampling clock in response to an optimum phase delay quantity which is an average of the first and second phase delay quantities.
REFERENCES:
patent: 6097444 (2000-08-01), Nakano
patent: 6268848 (2001-07-01), Eglit
patent: 6285344 (2001-09-01), Everard et al.
patent: 6340993 (2002-01-01), Hasegawa et al.
patent: 6724381 (2004-04-01), Sakashita
LandOfFree
Apparatus and method for controlling phase of sampling clock... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Apparatus and method for controlling phase of sampling clock..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus and method for controlling phase of sampling clock... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3585571