Apparatus and method for controlling enable time of signal...

Details Apparatus and method for controlling enable time of signal... Apparatus and method for controlling enable time of signal...

2007-01-18

2010-06-01

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C365S207000, C365S233110, C365S233120, C365S236000

Reexamination Certificate

active

07729196

ABSTRACT:
Disclosed is an apparatus for controlling an enable interval of a signal controlling an operation of data buses which connect a bit line sense amplifier with a data sense amplifier according to a variation of an operational frequency of a memory device. The apparatus comprises a pulse width control section for changing the pulse width of an input signal depending on the operational frequency of the memory device after receiving the input signal, a signal transmission section for buffering a signal outputted from the pulse width control section, and an output section for receiving a signal outputted from the signal transmission section so as to output a first signal for controlling the signal to control the operation of the data buses.

REFERENCES:
patent: 6842033 (2005-01-01), Kim et al.
patent: 2004/0042334 (2004-03-01), Sasaki et al.
patent: 2005/0257121 (2005-11-01), Kim et al.

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