Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2007-02-13
2007-02-13
Nguyen, Viet Q. (Department: 2827)
Static information storage and retrieval
Addressing
Sync/clocking
C365S189050, C327S299000
Reexamination Certificate
active
10876915
ABSTRACT:
Disclosed is an apparatus for controlling an enable interval of a signal controlling an operation of data buses which connect a bit line sense amplifier with a data sense amplifier according to a variation of an operational frequency of a memory device. The apparatus comprises a pulse width control section for changing the pulse width of an input signal depending on the operational frequency of the memory device after receiving the input signal, a signal transmission section for buffering a signal outputted from the pulse width control section, and an output section for receiving a signal outputted from the signal transmission section so as to output a first signal for controlling the signal to control the operation of the data buses.
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Kim Ji Hyun
Nam Young Jun
Hynix / Semiconductor Inc.
Nguyen Viet Q.
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