Apparatus and method for controlling clocking frequency in an in

Details Apparatus and method for controlling clocking frequency in an in Apparatus and method for controlling clocking frequency in an in

1996-12-31

1999-03-09

An, Meng-Ai T.

39575001, 39575002, 39575003, 39575006, G06F 132

Patent

active

058812970

ABSTRACT:
A method and apparatus for reducing power in a computer system having a counter and a phase generator. The method consists of receiving an input clock signal which has a plurality of clock cycles and receiving an enable signal. If the enable signal is active, then the counter performs a divide operation. In addition, a block signal is generated when the enable signal is active to hold the output signal in its present state. The block signal is removed if the divide operation is completed or if the enable signal becomes inactive. When the enable signal is not active, then the output signal generated is equal to and in phase with the input clock signal if the enable signal is not active.

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patent: 5586332 (1996-12-01), Jain et al.
patent: 5778237 (1998-07-01), Yamamoto et al.
patent: 5790877 (1998-08-01), Nishiyama et al.

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