Apparatus and method for controlling clock signal in...

Details Apparatus and method for controlling clock signal in... Apparatus and method for controlling clock signal in...

2007-12-18

2007-12-18

Elms, Richard T. (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S194000, C360S051000, C326S028000, C714S814000

Reexamination Certificate

active

11188715

ABSTRACT:
An operation clock controller for preventing a semiconductor memory device from operating when an operation frequency of an external clock is higher than a predetermined frequency. The operation clock controller includes a clock buffer for buffering an external clock to output an internal clock; a unit delaying set for sequentially delaying the internal clock to output a plurality of delayed clocks; a phase detecting block for detecting logic levels of the delayed clocks at a rising edge of the internal clock to output phase detecting signals; a sampling pulse generator for outputting a sampling signal generated at a predetermined point of the internal clock; a latching block for outputting a phase detection latch signal by sampling and latching the phase detection signal at a point of the sampling signal being inputted; and a frequency detection block for outputting the frequency detection signal by logically combining the phase detection latch signal.

REFERENCES:
patent: 5708624 (1998-01-01), Leung
patent: 5973989 (1999-10-01), Pawlowski
patent: 5999483 (1999-12-01), Itou
patent: 6857066 (2005-02-01), Bigbee et al.
patent: 2005/0246586 (2005-11-01), Chang
patent: 2006/0129867 (2006-06-01), Brodsky

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