Patent
1995-12-13
1998-09-08
Lee, Thomas C.
395849, G06F 300
Patent
active
058059253
ABSTRACT:
A data communications system (10) has a system management controller (100) and multiple data communications devices (21-1 through 21-n). The system management controller has a processor (110) and random access memory (115). The various data communications devices (21-1 through 21-n) are coupled to the system management controller (100) through a common address bus (12) and a common management bus (11). Through the processor (110), the system management controller (100) sequentially addresses each of the data communications devices (21-1 through 21-n) at a default data rate and determines a requested data rate for each device (FIG. 6, 305-333). The system management controller (100), through the processor (110), stores this requested data rate information, correlated with the address of each data communication device, in the random access memory (115) (FIG. 6, 305), and communicates with each such device at its requested data rate (FIG. 6, 335; FIG. 10, 500-545). In the event of errors, both the system management controller (100) and the addressed data communications device revert to a default data rate (FIG. 9, 435; FIG. 10, 525).
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Blackwell Steven R.
Gautreaux, II Richard A.
Reed Douglas D.
Chen Anderson I.
Gamburd Nancy R.
Lee Thomas C.
Motorola Inc.
Powell John W.
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