Apparatus and method for controlling a system bus of a multiproc

Details Apparatus and method for controlling a system bus of a multiproc Apparatus and method for controlling a system bus of a multiproc

1995-07-31

1996-03-19

Beausoliel, Jr., Robert W.

39518319, 39518209, 395163, G06F 1336, G06F 1100

Patent

active

055009450

ABSTRACT:
In a bus arbiter connected to a system bus of a multi-processor system having a plurality of modules respectively having processors, a first unit detects an abnormality in the multi-processor system on the basis of an internal state of the bus arbiter and a predetermined signal transferred via the system bus. A second unit initializes the internal state of the bus arbiter to restart the bus arbiter when the first unit detects an abnormality.

REFERENCES:
patent: 4085448 (1978-04-01), Kogge
patent: 4453215 (1984-06-01), Reid
patent: 4621322 (1986-11-01), Suzuki et al.
patent: 4825438 (1989-04-01), Bennett et al.
patent: 5146596 (1992-09-01), Whittaker et al.
patent: 5155843 (1992-10-01), Stamm et al.
patent: 5423030 (1995-06-01), Byers et al.

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