Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit
Reexamination Certificate
1999-10-28
2001-05-22
Nuton, My-Trang (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Particular stable state circuit
C327S212000
Reexamination Certificate
active
06236253
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates to electronic circuits, and particularly to self-timed circuits used in digital processing systems. The invention encompasses both an apparatus and method for controlling a reset in a self-timed circuit.
BACKGROUND OF THE INVENTION
An operation in an integrated circuit may be initiated following a certain delay after the occurrence of some triggering event. In digital processing systems, for example, a sense amplifier may be enabled to read data from a random access memory array after a delay measured from the activation of the word lines in the memory array. This type of circuit, in which one portion of the circuit is controlled by another portion in response to some triggering event, is commonly referred to as a self-timed circuit. Many types of circuits used in digital processors are commonly implemented as self-timed circuits.
Self-timed circuits are difficult to implement in certain cases. A multiple-clock system in which the clock signals may be underlapped presents one instance in which a self-timed circuit is difficult to implement. In an underlapped condition, a first clock signal ends before a second clock signal appears. If, for example, the first clock signal is used as an event to initiate the operation of a self-timed circuit, and if the result from the self-timed circuit must be available during the second clock signal, some mechanism must be employed to maintain the result from the self-timed circuit after the end of the first clock signal. That is, the result from the self-timed circuit must be maintained until some point after the second clock signal appears.
Properly maintaining the result from a self-timed circuit for a sufficient period of time is not a trivial task because the delay must allow for process variations. Simply gating the output from the self-timed circuit with the second clock signal would ensure that the self-timed circuit output was available during the second clock signal. However, gating the signal from the self-timed circuit with the second clock signal would at least slow the operation performed by the self-timed circuit.
SUMMARY OF THE INVENTION
It is an object of the invention to provide an apparatus and method for overcoming the above-described problems and others associated with self-timed circuits. In particular, it is an object of the invention to provide an apparatus and method for controlling the reset in a self-timed circuit such that the circuit is insensitive to an underlapped clock condition in a multiple-clock system.
An apparatus according to the invention utilizes a first latch circuit and a control latch circuit to control an additional circuit, such as a sense amplifier for example. The control latch circuit produces a reset control signal which is used to produce both a reset signal and a control output signal. The reset signal resets the first latch circuit, while the control output signal may be used to control the additional circuit even after the first latch circuit is reset.
The first latch circuit latches an initial signal which is produced in response to a first clock signal. This first latched signal or first latch output signal provides an input to the control latch circuit along with the second clock signal. Upon receipt of the second clock signal, the control latch circuit latches the first latch output signal to produce the reset control signal. This reset control signal is delayed through a reset arrangement preferably comprising a series of inverter circuits to produce the reset signal for resetting the first latch circuit.
One alternate form of the invention further includes a fast path circuit. This fast path circuit receives the control output signal and the first latch output signal as its inputs and produces a fast path output signal when at least one of the input signals is active. Since the first latch output signal always becomes active prior to the control. output signal, the fast path output signal is available earlier for controlling the operation of another circuit. Also, the fast path output signal is stable throughout the duration of the second clock signal. Thus, the fast path output is ideally suited for use as a sense enable signal for a sense amplifier which has its outputs latched on the second clock signal. The fast path signal may appear early to enable the sense amplifier, and remains stable throughout a second clock to ensure the sense amplifier results are valid when latched. That is, the fast path output signal becomes active during the first clock signal and remains active until the second clock signal goes inactive. This is the case even when the first and second clocks are underlapped, with the first clock signal ending prior to the start of the second clock signal.
These and other objects, advantages, and features of the invention will be apparent from the following description of the preferred embodiments, considered along with the accompanying drawings.
REFERENCES:
patent: 5867049 (1999-02-01), Mohd
patent: 5900759 (1999-05-01), Tam
patent: 5942919 (1999-08-01), Ang et al.
patent: 6144237 (2000-11-01), Ikezaki
Leasure Terry Lee
Paredes Jose Angel
Culbertson Russell D.
International Business Machines - Corporation
Nuton My-Trang
Salys Casimer K.
Shaffer & Culbertson LLP
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