Data processing: software development – installation – and managem – Software program development tool – Translation of code
Reexamination Certificate
1999-05-27
2001-10-23
Chaki, Kakali (Department: 2122)
Data processing: software development, installation, and managem
Software program development tool
Translation of code
C717S152000
Reexamination Certificate
active
06308323
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an apparatus and method for compiling a plurality of instruction sets for a processor. More particularly, the present invention relates to a compiling apparatus and method for compiling a plurality of instruction sets for a processor which has a function for selecting the most appropriate instruction set for achieving system efficiency.
The present invention further relates to a programmed media for recording the compiling method.
2. Discussion of the Related Art
Recent development of semiconductor technology provides a higher functional microprocessor, memory or a peripheral controlling LSI at a lower cost. This permits a higher functioned personal computer at a lower price. In particular, remarkable developments have been achieved for a microprocessor for mainly controlling a computer.
A processing width for the microprocessor has advanced from 16 bits to 32 bit. Recently, a super-functional microprocessor having a processing width of more than 64 bits and an operating speed of more than 200 MHZ frequency has been developed. Consequently, it has become possible to produce a higher functioned computer that loads a substantial operating system (OS) for using a lot of commercial software.
Among these higher functioned microprocessors, there is one type of microprocessor that has a plurality of instruction sets comprised of different lengths of instruction codes, i.e., 16 bits and 32 bits. In a compiling process for such a microprocessor having a plurality of instruction sets, a programmer needs to judge which one of the plurality of instruction sets is most appropriate for achieving the best efficiency for the system.
However, a conventional compiling method does not include information enabling advance selection of the most appropriate instruction set. In actual practice, a programmer evaluates performance after one of the plurality of instruction sets has once compiled. And if it does not meet to the required performance level, a further compiling process using another instruction set is executed to examine which instruction set is the most appropriate for compiling.
Thus, the conventional compiling process is a burdensome for a programmer. Further, it takes a long time to compile a plurality of instruction sets. Thus, the conventional process has the drawback of such inefficient compiling.
SUMMARY OF THE INVENTION
Apparatus and method according to the present invention solve the aforementioned problems and defects of a conventional compiling method for selecting the most appropriate instruction set among a plurality of them.
For achieving these and other advantages and in accordance with the present invention, there is provided a compiling method for a processor having a plurality of different instruction sets. The method comprises dividing a source program into a plurality of modules in accordance with a predetermined unit, compiling the respective modules with the respective ones of the plurality of instruction sets; providing data for evaluating performance and code size based upon the module compilations with the respective ones of the plurality of different instruction sets; and selecting an optimum instruction set among the plurality of different instruction sets by comparing the evaluation data.
Also in accordance with the present invention, there is provided a compiling method for a processor having a plurality of different instruction sets. The method comprises generating an intermediate code from a source program, and generating an object code by optimizing the intermediate code. Further, the generating of an intermediate code includes processing the source program by a plurality of analyzing steps. The method further includes executing an optimizing process that does not depend upon an instruction set for the intermediate code and storing a result of the optimizing process, and executing an optimizing process that depends upon the instruction set for generating an object code for each of the plurality of different instruction sets.
Further in accordance with the present invention there is provided compiling apparatus for a processor having a plurality of different instruction sets. The apparatus comprises means for dividing a source program into a plurality of modules in accordance with a predetermined unit, means for compiling the respective modules with respective ones of the plurality of different instruction sets, means for providing data for evaluating performance and code size based upon the module compilations with the respective ones of the plurality of different instruction sets and means for selecting an optimum instruction set among the plurality of different instruction sets by comparing the evaluation data.
Additionally in accordance with the present invention, there is provided a storage media for storing a compiling method for a processor having a plurality of different instruction sets comprising dividing a source program into a plurality of modules in accordance with a predetermined unit, compiling the respective modules with respective ones of the plurality of different instruction sets, providing data for evaluating performance and code size based upon the module compilations with the respective ones of the plurality of different instruction sets, selecting an optimum instruction set among the plurality of different instruction sets by comparing the evaluation data, inserting an instruction set changing command at a necessary portion for changing the instruction set, and outputting an object code in accordance with the selection.
REFERENCES:
patent: 5604905 (1997-02-01), Tevanian et al.
patent: 5787285 (1998-07-01), Lanning
patent: 5815721 (1998-09-01), Benitez
patent: 5835773 (1998-11-01), Dunn
patent: 5835775 (1998-11-01), Washington et al.
patent: 5854913 (1998-12-01), Goetz et al.
patent: 5987259 (1999-11-01), Goebel
patent: 6049668 (2000-04-01), Smith et al.
patent: 6067575 (2000-05-01), McManis et al.
patent: 6085307 (2000-07-01), Evory et al.
Hayashida et al., “Optimizing metod of C compiler for TRON architecture”, IEEE, 1992, pp 70-76.*
Cole, “integrated tools ease design”, Electronic Engineering Times, Dec. 1995, pp 24.
Chaki Kakali
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
LandOfFree
Apparatus and method for compiling a plurality of... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Apparatus and method for compiling a plurality of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus and method for compiling a plurality of... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2556946