Computer graphics processing and selective visual display system – Computer graphics processing – Graphic manipulation
Reexamination Certificate
2000-08-10
2003-07-22
Bella, Matthew C. (Department: 2676)
Computer graphics processing and selective visual display system
Computer graphics processing
Graphic manipulation
Reexamination Certificate
active
06597370
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a video monitor, and more particularly to an apparatus and a method for compensating a distorted clock phase.
2. Background of the Related Art
In general, a video monitor is an apparatus for displaying an image signal having an image mode such as SVGA (800×600), XGA (1024×768), SXGA (1280×1024), for example, which is transmitted from a main body connected to the monitor, after a series of signal processing. The main body is, for example, a video card of a work station or a personal computer.
Further, the monitor was originally based on a cathode-ray tube technology. Recently, a digital type monitor using an LCD as a typical plate type displaying element appropriate for a large sized monitor has been commercialized, as there is a tendency toward large sized display apparatus in response to the development of the modern technique.
A related art monitor, as shown in
FIG. 1
, includes a microcomputer
1
for determining an image mode according to a frequency of a horizontal synchronizing signal and a vertical synchronizing signal transmitted from a main body. The microcomputer outputs a control signal to perform a signal processing operation according to the image mode. Next, a Phase Locked Loop (PLL)
2
is provided for generating a clock pulse based on a control signal of the microcomputer
1
.
Also included is an A/D converter
3
for sampling R/G/B image signals transmitted from the main body according to the clock pulse provided by the PLL
2
. The A/D converter converts the analog image signals to digital signals. A scaler
4
is provided for adjusting a size of the digital R/G/B signals output from the A/D converter
3
to a frame unit, in response to the control signal of the microcomputer
1
by using the clock pulse provided by the PLL
2
.
Finally, a frame buffer memory
5
stores an output from the scaler
4
, and an LCD module
6
outputs the image signals stored in the frame buffer memory
5
according to the control signal of the microcomputer
1
.
The operation of the related art monitor as described above will be explained hereinafter.
First, the microcomputer
1
outputs a control signal to the PLL
2
. The PLL
2
, in turn, supplies a sampling clock corresponding to a frequency of horizontal/vertical synchronizing signals transmitted from the; main body to the A/D converter
3
and the scaler
4
. Specifically, the PLL
2
generates a clock pulse preset according to a control signal of the microcomputer to supply the clock pulse to the A/D converter
3
and the scaler
4
.
The A/D converter
3
samples the R/G/B image signals transmitted from the main body according to the sampling clock provided by the PLL
2
, and thus converts the analog image signals to digital signals to be output to the scaler
4
.
The scaler
4
then adjusts the size of the output of the A/D converter
3
according to a control signal of the microcomputer
1
, and stores the adjusted output of the A/D converter
3
to the frame buffer memory
5
. Then, the digital image signals thusly stored in the frame buffer memory
5
are displayed via a display module, such as the LCD module
6
.
The related art monitor as described above, however, has many disadvantages. For example, a user must manually reset the clock phase to compensate for distortion of the clock phase, which can occur due to a change of temperature. A distortion of the clock phase can occur in response to a change of ambient temperature, and can cause a distortion of a screen.
SUMMARY OF THE INVENTION
An object of the invention is to solve at least the above problems and/or disadvantages and to provide at least the advantages described hereinafter.
Another object of the present invention is provide an apparatus and a method for compensating a clock phase of a monitor that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
Another object of the present invention is to provide an apparatus and a method for compensating a clock phase of a monitor, in which an image data displayed on a screen is compared with a prescribed reference data and a detected distortion of a clock phase is automatically compensated.
Another object of this invention is to allow a normal screen to be displayed when distortion of a clock phase is generated.
Another object of the invention is to detect an abnormal state of the screen.
To achieve at least these or other advantages in whole or in parts, there is provided an apparatus for compensating a clock phase of a monitor, including a first memory for storing a reference digital data Vram, a PLL for generating a predetermined sampling clock synchronized with a horizontal synchronizing signal H-Sync and a vertical synchronizing signal V-Sync applied from a main body, an A/D converter for sampling an analogue image signal applied from the main body according to the sampling clock generated by the PLL to convert the analogue image signal to a digital image signal, a second memory for temporarily storing the digital image signal output from the A/D converter by a frame unit, a scaler for transferring the digital image signal, which is output from the A/D converter and stored in the second memory for constituting a frame, according to a signal input timing of a display module, and a microcomputer for extracting a digital data from the digital signal output from the scaler to control the PLL according to whether the extracted digital data is in coincidence with the reference data stored in the first memory.
Also, to achieve at least these advantages, in whole or in parts, there is provided a method for compensating a clock phase of a monitor having a PLL, including setting a reference digital data, displaying a clock phase adjusting bar corresponding to the preset reference digital data on an OSD, extracting a digital data A displayed on a current screen after a predetermined time period, adjusting an output phase of a clock pulse by controlling the PLL so that the reference digital data is in coincidence with the digital data A displayed on a current screen after determining whether the reference digital data is in coincidence with the digital image data A displayed on the current screen, and storing the adjusted clock phase value if the adjusted digital data A is in coincidence with the set reference digital data.
To further achieve the above-described objects of the present invention in a whole or in parts, there is provided a display apparatus that includes a first memory to store reference data, a clock generator to generate a sampling clock synchronized with at least one synchronizing signal, a converter to convert a first format image signal into a second format image signal according to the sampling clock, a second memory to store the second format image signal as a frame unit, a scaler to form and transfer the frame unit second format image signal to a display module, and a microcomputer to extract data from the second format signal outputted from the scaler, compare it to the reference data, and to control the clock generator according to a result of the comparison.
To further achieve the above-described objects of the present invention in a whole or in parts, there is provided a method for compensating a clock phase of a monitor that includes setting a reference data value, displaying a clock phase adjusting bar corresponding to the reference data on an on screen display (OSD), extracting image data displayed on a screen after a first prescribed time period, determining whether the reference data substantially equals the image data, adjusting an output phase of a clock pulse by controlling a clock pulse generator to modify the image data, so that it substantially equals the reference data, and storing the adjusted clock phase value if the adjusted image data substantially equals the reference data.
To further achieve the above-described objects of the present invention in a whole or in parts, there is provided a method of controlling a video
Bella Matthew C.
Fleshner & Kim LLP
LG Electronics Inc.
Rahmjoo Manucher
LandOfFree
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