Data processing: measuring – calibrating – or testing – Testing system – Of circuit
Reexamination Certificate
2006-03-27
2009-08-25
Nghiem, Michael P (Department: 2863)
Data processing: measuring, calibrating, or testing
Testing system
Of circuit
C702S089000
Reexamination Certificate
active
07580806
ABSTRACT:
An apparatus and method for compensating clock period elongation during scan testing in an integrated circuit (IC) includes operating a clock associated with the IC at a frequency (fTARGET) at which IC operation is sought to be determined, measuring the actual clock period (TCLOCK—OUT) at a clock output, scan testing the IC, measuring the actual clock period (TSCAN—CLOCK—OUT) at the clock output, determining a delay by calculating the difference between TSCAN—CLOCK—OUTand TCLOCK—OUT, and compensating for the delay by increasing the clock frequency during scan test.
REFERENCES:
patent: 5254942 (1993-10-01), D'Souza et al.
patent: 5428626 (1995-06-01), Frisch et al.
patent: 5703489 (1997-12-01), Kuroe
patent: 5933039 (1999-08-01), Hui et al.
patent: 5935256 (1999-08-01), Lesmeister
patent: 5978942 (1999-11-01), Rockoff
patent: 6256760 (2001-07-01), Carron et al.
patent: 6320436 (2001-11-01), Fawcett et al.
patent: 6442722 (2002-08-01), Nadeau-Dostie et al.
patent: 6484294 (2002-11-01), Kiyoshige et al.
patent: 6763485 (2004-07-01), Whetsel
patent: 6907556 (2005-06-01), Siegel
patent: 6934921 (2005-08-01), Gu et al.
patent: 6948096 (2005-09-01), Parvathala et al.
patent: 6995554 (2006-02-01), Loke et al.
patent: 7079973 (2006-07-01), Rodgers et al.
patent: 7123001 (2006-10-01), Loke et al.
patent: 7516379 (2009-04-01), Rohrbaugh et al.
patent: 2002/0105337 (2002-08-01), Coates et al.
patent: 2002/0157050 (2002-10-01), Whetsel
patent: 2002/0184584 (2002-12-01), Taniguchi et al.
patent: 2003/0188243 (2003-10-01), Rajan
patent: 2004/0085082 (2004-05-01), Townley
patent: 2004/0193981 (2004-09-01), Clark et al.
patent: 2005/0222795 (2005-10-01), Rodgers et al.
patent: 2005/0229056 (2005-10-01), Rohrbaugh et al.
patent: 1 584 940 (2005-10-01), None
Almy, Thomas , “Making Precise At-Speed Timing Measurements Via Boundary-Scan”,IEEE Custom Integrated Circuits Conference1997, 207-209.
IBM Technical Disclosure Bulletin, , “NN8006328 Zero Display Set Reset Latch with Edge-Triggered Strobe Control”, Jun. 1980, 328-329.
Groth Cory D.
Rearick Jeffrey R.
Rodgers Richard S.
Avago Technologies General IP ( Singapore) Pte. Ltd.
Nghiem Michael P
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