Apparatus and method for compensating clock period...

Details Apparatus and method for compensating clock period... Apparatus and method for compensating clock period...

2006-07-18

2006-07-18

Nghiem, Michael (Department: 2863)

Data processing: measuring, calibrating, or testing

Testing system

Of circuit

Reexamination Certificate

active

07079973

ABSTRACT:
An apparatus and method for compensating clock period elongation during scan testing in an integrated circuit (IC) includes operating a clock associated with the IC at a frequency (fTARGET) at which IC operation is sought to be determined, measuring the actual clock period (TCLOCK_OUT) at a clock output, scan testing the IC, measuring the actual clock period (TSCAN_CLOCK_OUT) at the clock output, determining a delay by calculating the difference between TSCAN_CLOCK_OUT and TOLOCK_OUT, and compensating for the delay by increasing the clock frequency during scan test.

REFERENCES:
patent: 6320436 (2001-11-01), Fawcett et al.
patent: 6442722 (2002-08-01), Nadeau-Dostie et al.
patent: 2005/0229056 (2005-10-01), Rohrbaugh et al.
patent: 1 584 940 (2005-10-01), None

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