Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2001-06-30
2003-10-28
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S205000
Reexamination Certificate
active
06639438
ABSTRACT:
FIELD OF THE INVENTION
The field of invention relates to data signal processing generally; and more specifically, to compensating for the skew that exists between a clock signal and a data signal.
BACKGROUND
FIG. 1
shows a pair of semiconductor chips
101
,
102
coupled together by a serial link
110
having a data signal line
103
and a clock signal line
104
. The transmitting unit
101
sends a data signal
105
to the receiving unit
102
along data signal line
103
. The receiving unit
102
uses a clock signal
106
that is sent along clock signal line
104
to receive the data
105
.
That is, in the example of
FIG. 1
, the receiving unit
102
clocks the data signal
105
on the rising edge of the clock signal
106
. The clock signal
106
may be referred to as a quadrature clock because the phase of its rising edges are 90 degrees away from the rising edges of the data signal
105
(using the data signal
105
as a phase reference). A link that transmits a clock along with data may be referred to as a source synchronous interface. Various source synchronous interfaces exist such as, for example, Low Voltage Differential Signalling (LVDS) or Serial Gigabit Media Independent Interface (SGMII).
A problem with serial links, particularly as their frequency of operation rises, is the presence of skew
109
between a data signal
107
and a clock signal
108
when it is received at the receiving unit. Skew
109
is any phase relationship between the edges of the data signal
107
and clock signal
108
other than the nominal or “designed for” phase relationship (such as 90 degrees, using the data signal
105
as a phase reference).
Skew may arise because the transfer function and/or trace length of the data signal line
103
is different than the transfer function and/or trace length of the clock signal line
104
. For example if the data signal line
103
is shorter or has less capacitance than the clock signal line
103
, the rising edges of the clock signal
108
can have more than 90 degrees of phase shift with respect to the rising edges of the data signal
107
.
For a given difference in transfer function and/or trace length between the data and clock signal lines
103
,
104
, greater skew is observed between the data signal
107
and clock signal
108
as the frequency of operation of the serial link
110
increases. That is, the differences between the signal lines
103
,
104
have an effect on the delay of the signals as they propagate from the transmitting unit
101
to the receiving unit
102
. As the frequency of the serial link's operation rises, the delay represents a greater percentage of the data signal's pulse widths.
As skew
109
increases the performance of the serial link degrades. That is, because the receiving unit
102
uses the clock signal to clock the reception of the data carried by the data signal
107
, the “misposition” of the clock signal
108
edges causes the receiving unit
102
to consistently clock incorrect data.
REFERENCES:
patent: 6300816 (2001-10-01), Nguyen
Glenn Robert C.
Ranganathan Sumant
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Wells Kenneth B.
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