Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
2001-08-14
2002-09-03
Williams, Howard L. (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S143000, C327S096000, C327S337000, C327S554000
Reexamination Certificate
active
06445331
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to switched capacitor circuits. More particularly, the present invention relates to an apparatus and method that reduces the requirements and number of voltage references that are necessary for proper operation in a switched capacitor circuit while maintaining an optimized common-mode input voltage.
BACKGROUND OF THE INVENTION
A one-bit over-sampling analog-to-digital converter (
600
) is depicted in FIG.
6
. This type of analog-to-digital converter (ADC) is often referred to as a first order delta-signal (&Dgr;&Sgr;) modulator. As shown in the figure, the first order &Dgr;&Sgr;-modulator (
600
) includes a summer (
601
), an integrator (
602
), a 1-bit ADC (
603
) a digital low pass filter (
604
), and a 1-bit digital-to-analog converter (
605
). The first order &Dgr;&Sgr;-modulator (
600
) receives an analog signal and produces an N-bit digital code output.
In operation, an analog signal and an output of 1-bit digital-to-analog converter (DAC)
605
are fed into summer
601
. The summer (
601
) provides an output that corresponds to the difference between the analog input signal and the output of DAC
605
. The integrator (
602
) provides an integration signal in response the difference signal. The 1-bit ADC (
603
) produces a digital bit by converting by comparing the integration signal to a predetermined threshold level (i.e., mid-supply level). This digital bit is fed into the 1-bit DAC, which produces an analog voltage that corresponds to one of two voltages (i.e., +VREF and -VREF). Digital low pass filter (LPF)
604
receives the digital bit from the 1-bit ADC (
603
) and produces an N-bit digital code output.
SUMMARY OF THE INVENTION
The present invention is directed to switched capacitor circuits. More particularly, the present invention relates to an apparatus and method for a switched capacitor integrator that includes common-mode input voltage regulation.
Briefly described below is an apparatus and method for an improved integrator that provides for a regulated common-mode voltage. The improved integrator is arranged as a switched capacitor circuit that includes a differential amplifier. The common-mode input voltage of the differential amplifier is regulated by proper arrangement of the switched capacitor circuit. By regulating the common-mode input voltage, the performance of the differential amplifier is improved. Since the common-mode input voltage is regulated, it is possible to operate the improved integrator at power supply levels below 2V. The improved integrator operates with three single-ended reference signals such that the integrator design is simplified and overall costs are reduced. Capacitor ratios may be adjusted to scale the input common-mode voltage of the differential amplifier. The improved integrator may be arranged as a delayed integrator or a non-delayed integrator by changing the control signals on the switches. The improved integrator may be used in a &Dgr;&Sgr;-modulator.
An apparatus for controlling a common-mode input voltage for a differential amplifier, where the differential amplifier includes a first input terminal and a second input terminal is also described below. The apparatus includes a first and second reference capacitance circuit, and a first and second input capacitance circuit. First and second switching circuits are arranged to initialize the first and second reference capacitance circuits, respectively, to a first potential when the apparatus is in a sample mode. Third and fourth switching circuit are arranged to initialize the first and second input capacitance circuits, respectively, to a second potential when the apparatus is in the sample mode. A fifth switching circuit is arranged to couple a first reference signal to the first reference capacitance circuit when the apparatus is in a hold mode. A sixth switching circuit is arranged to couple a second reference signal to the second reference capacitance circuit when the apparatus is in the hold mode. A seventh switching circuit is arranged to couple the first reference capacitance circuit and the first input capacitance circuit to the first input of the differential amplifier when the apparatus is in the hold mode. An eighth switching circuit is arranged to couple the second reference capacitance circuit and the second input capacitance circuit to the second input of the differential amplifier when the apparatus is in the hold mode. The common-mode input voltage of the differential amplifier is determined by at least the first reference signal, the second reference signal, and a third reference signal. The first potential is determined by two of the first, second, and third reference signals, while the second potential is determined by at least one of the first, second, and third reference signals.
In one example, a method for controlling a common-mode input voltage for a differential amplifier in a switched capacitor circuit is described below. The method includes initializing first and second reference capacitors to a first potential during a sampling mode, coupling one of a first reference signal and a second reference signal to the first capacitor during a hold mode, coupling another of the first reference signal and a second reference signal to the second capacitor during the hold mode, initializing first and second input capacitors to a second potential during the sampling mode, coupling the first reference capacitor and the first input capacitor to a first input of the differential amplifier during the hold mode, coupling the second reference capacitor and the second input capacitor to a second input of the differential amplifier during the hold mode, redistributing charge stored on the first reference capacitor and the first input capacitor during the hold mode, and redistributing charge stored on the second reference capacitor and the second input capacitor during the hold mode, such that the common-mode input voltage of the differential amplifier is determined by the redistribution of charges.
In another example, an apparatus for regulating a common-mode input voltage for a differential amplifier in a switched capacitor circuit is described below. The apparatus includes a first means for initializing that is arranged to initialize first and second reference capacitors to a first potential during a sampling mode. A first means for selectively coupling is arranged to selectively couple one of a first reference signal and a second reference signal to the first capacitor, and to selectively couple the other of the first and second reference signals to the second reference capacitor, during a hold mode. A second means for initializing is arranged to initialize first and second input capacitors to a second potential during the sampling mode. A second means for selectively coupling is arranged to couple the first reference capacitor and the first input capacitor to a first input of the differential amplifier during the hold mode. Charges on the first reference capacitor and the first input capacitor are redistributed. A third means for selectively coupling is arranged to couple the second reference capacitor and the second input capacitor to a second input of the differential amplifier during the hold mode. Charges on the second reference capacitor and the second input capacitor are redistributed. The redistribution of charges on the reference capacitors and the input capacitors are utilized to adjust the common-mode input voltage of the differential amplifier.
A more complete appreciation of the present invention and its improvements can be obtained by reference to the accompanying drawings, which are briefly summarized below, to the following detailed description of illustrative embodiments of the invention, and to the appended claims.
REFERENCES:
patent: 5057839 (1991-10-01), Koch
patent: 5617093 (1997-04-01), Klein
patent: 5691720 (1997-11-01), Wang et al.
Hertzberg Brett A.
Merchant & Gould P.C.
National Semiconductor Corporation
Williams Howard L.
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