Apparatus and method for cipher processing system using...

Cryptography – Communication system using cryptography – Time segment interchange

Reexamination Certificate

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C380S028000

Reexamination Certificate

active

06990199

ABSTRACT:
An encryption processing system implements an encryption algorithm using a memory system comprising a multiple-port memory by performing at least one set of parallel read and write operations to the memory. The algorithm is, for example, the conventional ARCFOUR (or RC4) algorithm, and the key and state array used in the ARCFOUR algorithm are stored in the multiple port memory. During execution of the ARCFOUR algorithm, a read from one port of the multiple port memory of a state array value is done while another port is used to write a new value to the state array. The use of such parallel read and write operations uses a comparator system that determines whether to use certain previously-read values from the state array or to read a new value from the state array when selecting the pseudorandom K byte to calculate the output data byte.

REFERENCES:
patent: 6088800 (2000-07-01), Jones et al.
patent: 6226742 (2001-05-01), Jakubowski et al.
patent: 1 191 739 (2002-03-01), None
Kundarewich P. “A CPLD-based RC-4 Cracking System” 1999 IEEE Canadian Conference on Electrical and Computer Engineering, Edmonton, Alberta, Canada, May 9-12, 1999, pp. 397-402.
K. Kaukonen et al., “A Stream Cipher Encryption Algorithm “Arcfour”” Internet-Draft, Internet Engineering Task Force, Jul. 14, 1999, pp 1-14.

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