Abrading – Abrading process – Glass or stone abrading
Reexamination Certificate
1999-09-03
2002-04-09
Eley, Timothy V. (Department: 3723)
Abrading
Abrading process
Glass or stone abrading
C451S063000, C451S288000, C451S398000
Reexamination Certificate
active
06368189
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to polishing and planarization of substrates including semiconductor materials, and more particularly to a polishing head in which the polishing or planarization pressure is applied by a pneumatic force directly against the backside of the substrate.
BACKGROUND
Modem integrated circuits have literally millions of active devices such as transistors and capacitors formed in or on a semiconductor substrate and rely upon an elaborate system of metalization, typically comprising multi-level metalization interconnections, in order to connect the active devices into functional circuits. An interlayer dielectric such as silicon dioxide is formed over a silicon substrate, and electrically isolates a first level of metalization which is typically aluminum from the active devices formed in the substrate. Metalized contacts electrically couple active devices formed in the substrate to the interconnections of the first level of metalization. In a similar manner metal vias electrically couple interconnections of a second level of metalization to interconnections of the first level of metalization. Contacts and vias typically comprise a metal such as tungsten surrounded by a barrier metal such as titanium-nitride. Additional layers can be stacked to achieve the desired (multi-layer) interconnection structure.
High density multilevel interconnections require the planarization of the individual layers of the interconnection structure and very little surface topography variation. Non-planar surfaces create poor optical resolution for the photo lithographic procedures used to lay done additional layers in later processing steps. Poor optical resolution prevents the printing of high density lines required for high density circuit and interconnect structures. Another problem associated with surface topography variation pertains to the ability of subsequent metalization layers to cover or span the step height. If a step height is too large there is a potential danger that open circuits will be created causing failure of the chip on which the open circuit occurs. Planar interconnect surface layers are a must in the fabrication of modem high density multilevel integrated circuits.
Planar substrate topography may be achieved using chemical-mechanical polishing (CMP) techniques. In conventional CMP systems and methods a silicon wafer is placed face down on a rotatable surface or platen covered with a flat polishing pad onto which a coating or layer of an active slurry has been applied. A substrate carrier formed from a rigid metal or ceramic plate mounts the backside of the wafer and applies a downward force against the backside of the wafer so that the front side is pressed against the polishing pad. In some systems, the downward force is generated mechanically such as via a mechanical weight, however, frequently, the downward force is communicated to the substrate carrier via a pneumatic source such as air or other fluid pressure. A resilient layer, often referred to as an insert, such as may be provided by a polymeric material, wax, or other cushioning material may frequently be used between the wafer mounting surface on the carrier and the backside of the wafer. The downward polishing force is communicated through the insert.
A retaining ring circumscribing the periphery of the wafer carrier and the wafer centers the wafer on the carrier and keeps the wafer from slipping out from alignment with the carrier. The carrier which mounts the wafer is coupled to a spindle shaft which is rotated via coupling to a motor. The downward polishing force combined with the rotational movement of pad together with the CMP slurry facilitate the abrasive polishing and planar removal of the upper surface of a thin film or layer from the front side surface of the wafer.
These conventional systems and methods present at least two problems or limitations. A first problem is that an unequal polishing pressure distribution can develop across the surface of the wafer as it is polished either as a result of mechanical misalignments in the carrier or polishing head assembly, interaction of the wafer front side surface with the polishing pad and slurry, nonuniformity of the insert, contamination introduced between the insert and the wafer backside surface such as polishing debris, or a variety of other of sources of polishing force nonuniformity that affect the planarization of the wafer substrate.
The properties of the insert are particularly problematic. While the CMP equipment manufacturer may design and fabricate a device having great precision and process repeatability, it is frequently found that the physical characteristics of the polymeric inserts which must be replaced after some predetermined number of wafers have been processed, and varies from batch to batch. Furthermore, event within a single batch, the characteristics will vary with the amount of water absorbed by the insert. Even more troublesome, different portions of the same insert may be drier or wetter than other areas thereby introducing polishing variations across the surface of each wafer.
A second problem associated with conventional CMP systems and methods is that even to the extent that uniform or substantially uniform polishing pressure may be achieved, see for example copending U.S. patent application Ser. No. 09/261,112 filed Mar. 3, 1999 for a Chemical Mechanical Polishing Head Assembly Having Floating Wafer Carrier and Retaining Ring, and U.S. patent application Ser. No. 09/294,547 filed Apr. 19, 1999 for a Chemical Mechanical Polishing Head Having Floating Wafer Retaining Ring and Wafer Carrier With Multi-Zone Polishing Pressure Control, each of which are assigned to Mitsubishi Materials Corporation, the same assignee as the instant application, and hereby incorporated by reference uniform polishing pressure may not always be the optimum polishing pressure profile for planarization of the wafer. This apparent paradox between the assumed desirability of a uniform polishing pressure and the need for a non-uniform polishing pressure arises from non-uniform layer deposition effects during the deposition process. To the extent that the deposited layer thickness varies in a known manners such as the radially varying thickness that is frequently encountered, the polishing pressure may desirably be varied to compensate for the deposition irregularities.
The pressure at any point on the front side surface of the wafer is largely is controlled by the local compressive modulus (hardness) and local compression of polishing pad, insert, and any other materials (desired or not) interposed between the source of the pressure and the contact point between the wafer and the polishing pad including the layers between the polishing pad and the generally hard rigid polishing table or platen. Any variation in the amount of compression of these elements results in local pressure variations at the polishing interface.
In general, all other factors being equal (e.g. same slurry composition, same effective linear speed of the wafer across the pad, etc.) the polish removal rate in chemical-mechanical polishing systems is proportional to the pressure applied between the wafer and the polishing pad in the direction perpendicular to the polishing motion. The greater the pressure, the greater the polish removal rate. Thus, nonuniform pressure distribution across the surface of the wafer tends to create a nonuniform polish rate across the surface of wafer. Nonuniform polishing can result in too much material being removed from some parts of wafer and not enough material being removed from other parts, and also cause formation of overly thin layers and/or result in insufficient planarization, both of which degrade semiconductor wafer process yield and reliability.
The nonuniform polishing may be particularly prevalent at the peripheral edge of the wafer where the sharp transition edge effects occur. In traditional approaches, a sharp transition exists between the portion of the polishing pad that is in contact with the poli
Charif Malek
Chin Scott
Kajiwara Jiro
Maloney Gerard S.
Price Jason
Flehr Hohbach Test Albritton & Herbert LLP
Mitsubishi Materials Corporation
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