Apparatus and method for capacitor coupled complementary bufferi

Details Apparatus and method for capacitor coupled complementary bufferi Apparatus and method for capacitor coupled complementary bufferi

1987-03-03

1989-01-17

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307544, 307551, 307565, 307448, H03K 1710, H03K 17687, H03K 19003, H03K 1704

Patent

active

047989726

ABSTRACT:
A semiconductor buffer circuit and buffering method for driving capacitive loads that enhances the current sinking and sourcing drive characteristics at times when the input signal is changing. Two transistors are used, a source follower and a current source pull-down, with an input signal applied to the control input of the source follower transistor. The complement of the input signal is capacitively coupled to the control input of the current source pull-down transistor. As a result, changes in the input voltage increase or decrease the conductivity of the current source pull-down transistor, thereby allowing the capacitive load to be charged and discharged more efficiently.

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R. L. Van Tuyl et al., "High-Speed Integrated Logic With GaAs MESFET's," IEEE Journal of Solid State Circuits, vol. SC-9, No. 5, pp. 269-276.
R. C. Eden et al., "Low Power GaAs Digital ICs Using Schottky Diode-FET Logic," ISSCC Digest of Technical Papers, pp. 68-69.
S. Katsu et al., "A GaAs Monolithic Frequency Divider Using Source Coupled FET Logic," IEEE Electron Device Letters, vol. Ed 1-3, No. 8.

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