Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – Unwanted signal suppression
Reexamination Certificate
2000-06-06
2002-02-05
Zweizig, Jeffrey (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
Unwanted signal suppression
Reexamination Certificate
active
06344772
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to apparatus and methods for realizing large values of capacitance using small valued capacitors.
In many circuits it is required and/or necessary to have large values of capacitance. However, to produce large values of capacitance in, and on, an integrated circuit (IC) normally requires that an unduly large portion of the available area of the IC chip be devoted to the capacitor. This presents a problem where it is desired and/or necessary to manufacture most, if not all, of the components of a complex circuit on the same IC chip to meet, among others, requirements for greater reliability, better component matching and lower noise.
A possible solution to the problem of insufficient on-chip capacitance may include the use of a known capacitance multiplication circuit
50
as shown in FIG.
1
. The circuit
50
includes a capacitor C1 connected between nodes
142
and
143
. The capacitance of C1 is effectively increased by means of amplifying the signal at node
142
(one side of C1) and supplying an amplified signal at node
143
(the other side of C1), whereby the effective capacitance of C1 is increased. The circuit
50
includes a buffering unity gain amplifier A
11
connected at its input to node
142
and at its output to an input
152
of amplifier
51
. Amplifier
51
includes a resistor R10 connected between input terminal
152
and an inverting input
153
of an operational amplifier A
12
. A feedback resistor R20 is connected between the output of A
12
and inverting input
153
. The gain, K, of amplifier
51
is substantially equal to R20/R10; with R20 selected to be greater than R10. The output of amplifier
51
is connected to node
143
. Due to the amplification of amplifier
51
, the effective capacitance of C1 at node
142
is multiplied by a factor of (1+K), whereby the effective capacitance at node
142
is equal to (1+K)(C1).
However, the circuit of
FIG. 1
suffers from certain significant problems. One problem is that the amplifiers, in particular operational amplifier A
12
, requires a large dynamic range. This may be illustrated by noting that if: (a) the input signal has a dynamic range between zero and 1 volt, and (b) a capacitance multiplication factor of 10 is desired, then amplifier A
12
must have a gain of 10 and a dynamic range between 0 and 10 volts. But, in integrated circuits operated at a power supply (operating) voltage between 1 and 5 volts, a dynamic range in excess of the power supply voltage can not be achieved. Another problem is that the gain bandwidth product of amplifier A
12
has to be K times the bandwidth of the input signal. Where the bandwidth of the input signal is in the range of 5 MHz, and K is 10, the gain bandwidth of amplifier A
12
would have to be in the range of 50 MHz. This high gain bandwidth product can normally be achieved only at the cost of significant power dissipation. This is a significant disadvantage in the manufacture of high density integrated circuits (ICs). Therefore, the prior art scheme for increasing the effective capacitance, just described, as well as other known schemes relying on the Miller effect to increase capacitance are not well suited for integrated circuits having small operating voltages and where low power dissipation is desired.
SUMMARY OF THE INVENTION
In circuits embodying the invention, the capacitance, C, of a capacitor is effectively increased by controlling the division of a signal current between a first path including the capacitor for carrying 1/X of the signal current and a second path for carrying the remainder (1−1/X) of the signal current; where X is normally greater than 2. A unity gain amplifier, having an input and an output, is connected at its input to the first path and at its output to the second path to ensure the continued division of the signal current, whereby the signal sees an effective capacitance which is approximately equal to C times (X).
In a particular embodiment a signal current, I, is supplied to a first node. The first path includes a first resistor (R1) connected between the first node and an intermediate node, and a first capacitor (C1) connected between the intermediate node and a point of reference potential. A unity gain amplifier has an input connected to the intermediate node and has an output at which it produces an output voltage equal to the one at the intermediate node. The second path includes a second resistor (R2) connected between the first node and the output of the unity gain amplifier, whereby the voltage drop across R1 is equal to the voltage drop across R2. For this circuit configuration, the effective value of the capacitor is equal to (C1)(1+R1/R2). Accordingly, C1 will be multiplied by the extent to which R1 is made larger then R2. In integrated circuits, resistors R1 and R2 can be made to have a wide range of values and the ratio of R1 to R2 can be readily controlled. Thus large effective values of capacitance, not readily formed in integrated circuit, may be obtained from small capacitors which are easily and readily formed in integrated circuits.
The capacitance multiplying network of the invention is well suited for use as a filter in many different system and circuit applications. For example, in a phase locked loop (PLL) circuit, a capacitance multiplying network may be advantageously connected to the output of a charge pump circuit for controlling the voltage applied to a voltage controlled oscillator (VCO).
REFERENCES:
patent: 5382918 (1995-01-01), Yamatake
patent: 6201438 (2001-03-01), Nicollini et al.
Agere Systems Guardian Corp
Schanzer, Esq Henry I.
Zweizig Jeffrey
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