Apparatus and method for calibrating the frequency of a...

Details Apparatus and method for calibrating the frequency of a... Apparatus and method for calibrating the frequency of a...

2005-07-07

2009-06-02

Payne, David C (Department: 2611)

Pulse or digital communications

Synchronizers

C375S316000, C375S295000, C375S219000, C327S165000, C327S166000, C327S176000, C370S395620, C398S155000, C714S020000

Reexamination Certificate

active

07542533

ABSTRACT:
Embodiments of the invention include an apparatus and method for continuously calibrating the frequency of a clock and data recovery (CDR) circuit. The apparatus includes a delay arrangement that generates a gating signal, and a gated voltage-controlled oscillator that is enabled by the gating signal. The gated voltage-controlled oscillator generates a recovered clock signal that is based on the data signal input to the CDR circuit. The apparatus also includes a frequency control loop that continuously calibrates the gated voltage-controlled oscillator in such a way that the frequency of the clock signal generated by the gated voltage-controlled oscillator continues to be one half of the period of the data bits in the input data signal and the clock signal remains synchronized to the center of the data state transitions of the input data signal. Alternatively, a secondary frequency control loop adjusts the amount of delay in the frequency control loop.

REFERENCES:
patent: 5237290 (1993-08-01), Banu et al.
patent: 5834980 (1998-11-01), Pitio et al.
patent: 6377082 (2002-04-01), Loinaz et al.
patent: 2004/0052316 (2004-03-01), Choi et al.
patent: 2006/0031701 (2006-02-01), Nam et al.
patent: 2006/0115035 (2006-06-01), Yu et al.

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