Electrical computers and digital processing systems: processing – Instruction fetching
Reexamination Certificate
2007-01-02
2007-01-02
Fleming, Fritz (Department: 2181)
Electrical computers and digital processing systems: processing
Instruction fetching
C712S218000
Reexamination Certificate
active
10422057
ABSTRACT:
An instruction buffering apparatus is disclosed. The apparatus includes an early queue and a late queue. The early queue receives an instruction generated during a first clock cycle. The late queue receives information related to the instruction during a second clock cycle subsequent to the first clock cycle. The early queue receives load/shift control signals for loading/shifting the early queue. Registers receive the early queue load/shift signals and provide delayed versions of the signals to the late queue for controlling loading/shifting the related information in the late queue. The late queue is configured such that when the apparatus is empty, the related information may be provided during the second clock cycle, i.e., in the same clock cycle that its related instruction is provided from the early queue.
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Davis E. Alan
Fleming Fritz
Huffman James W.
IP-First LLC
moll Jesse
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