Apparatus and method for booting a multiple processor system hav

Details Apparatus and method for booting a multiple processor system hav Apparatus and method for booting a multiple processor system hav

1992-10-30

1995-09-05

Kriess, Kevin A.

Boots, shoes, and leggings

3642281, 364DIG1, 364271, 3642434, 364270, 3642283, 39520019, G06F 1516, G06F 900

Patent

active

054487161

ABSTRACT:
An architecture and method for booting a multi-processor system having processor local memory and shared global memory, with shared global memory access managed by an atomic memory access controller and cache coherence managed by software. Reset circuits are used to synchronize to a master clock a commonly distributed start signal and processor individualized restart sequences, which reset circuit signals are distributed to reset both local and global memory. Global memory testing is assigned to a processor based upon its rate status in completing an internal test sequence. The systems and methods are particularly suited to booting a group of multiple but relatively independent processors. Furthermore, the practice of the invention facilitates booting of such system when one or more of the processors have been disconnected or failed.

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IBM Technical Disclosure Bulletin, vol. 33, No. 9, Feb. 1991-"System Support for Multiprocessing Without An Atomic Storage", pp. 18-23.

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