Apparatus and method for automatically placing ties and connecti

Details Apparatus and method for automatically placing ties and connecti Apparatus and method for automatically placing ties and connecti

1996-02-07

1999-05-04

Teska, Kevin J.

Boots, shoes, and leggings

364489, 364490, 364488, G06F 1700, G06F 1750

Patent

active

059010657

ABSTRACT:
Methods (100, 200, 250) and data processing system (300) for automatically placing ties (136, 138, 146, 148) and connection elements within an integrated circuit (120). Integrated circuit dimensions (102), element locations and element dimensions (104), and tie placement rules (106) are received for a particular integrated circuit (120). The quantities are then processed to place ties within the integrated circuit (108). Tie placement rules include tie spacings (164, 166), well edge spacings (162), and diffusion spacings (168) to prevent SCR latch up and gate threshold voltage drift. Tie placement methods (100, 200) automatically place ties within the integrated circuit (120) to comply with tie spacing rules and also consider estimated compactions so that tie numbers are minimized. Associated data processing system (300) and computer readable medium operate in conjunction with the methods of the present invention. A method of making an integrated circuit (350) optimally places ties and connection elements within an integrated circuit design.

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Chen et al. "Optimization of Quarter Micron MOSFETs for Low Voltage/Low Power Applications," IEEE, pp. 3.3.1-3.3.4, Dec. 1995.
Tsui et al. "Study of BiMOS Logic Gate Configuration for Improved Low-Voltage Performance," IEEE, pp. 371-374, Mar. 1993.

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