Boots – shoes – and leggings
Patent
1994-05-04
1997-05-27
Teska, Kevin J.
Boots, shoes, and leggings
364488, 371 27, 395500, G06F 11263, G06F 9455
Patent
active
056338139
ABSTRACT:
An electronic circuit test vector generation and fault simulation apparatus is constructed with programmable logic devices (PLD) or field programmable gate array (FPGA) devices and messaging buses carrying data and function calls. A test generation and fault simulation (TGFS) comparator is implemented in the PLD or FPGA consisting of a partitioned sub-circuit configuration, and a multiplicity of copies of the same configuration each with a single and different fault introduced in it. The method for test vector generation involves determining test vectors that flag each of the fault as determined by a comparison of the outputs of the good and single fault configurations. Further the method handles both combinational as well as sequential type circuits which require generating a multiplicity of test vectors for each fault. The successful test vectors are now propagated to the inputs and outputs of the electronic circuit, through driver and receiver sub-circuits, modeled via their corresponding TGFS comparators, by means of an input/output/function messaging buses. A method of fault simulation utilizing the TGFS comparators working under a fault specific approach determines the fault coverage of the test vectors.
REFERENCES:
patent: 3492572 (1970-01-01), Endicott et al.
patent: 3961250 (1976-06-01), Snethen
patent: 4242751 (1980-12-01), Henckels et al.
patent: 4862399 (1989-08-01), Freeman
patent: 4937765 (1990-06-01), Shupe et al.
patent: 4937827 (1990-06-01), Beck et al.
patent: 5058112 (1991-10-01), Namitz et al.
patent: 5177440 (1993-01-01), Walker, III et al.
patent: 5184308 (1993-02-01), Nagai et al.
patent: 5253181 (1993-10-01), Marui et al.
patent: 5257268 (1993-10-01), Agrawal et al.
patent: 5353289 (1994-10-01), Ohkawa
patent: 5384275 (1995-01-01), Sakashita
patent: 5386550 (1995-01-01), Yumioka et al.
patent: 5425036 (1995-06-01), Liu et al.
patent: 5452227 (1995-09-01), Kelsey et al.
Chow Peter
Frejd Russell W.
Teska Kevin J.
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