Data processing: artificial intelligence – Knowledge processing system
Reexamination Certificate
2000-04-13
2003-11-04
Starks, Jr., Wilbert L. (Department: 2121)
Data processing: artificial intelligence
Knowledge processing system
C717S156000
Reexamination Certificate
active
06643630
ABSTRACT:
TECHNICAL FIELD
This invention pertains to digital data processing and compiler systems. More particularly, this invention relates to techniques for performing an estimation of an optimized assembly code from the C code of an application that is delivered to a C compiler.
BACKGROUND OF THE INVENTION
The programming of digital signal processor (DSP) applications in high level languages such as C is becoming more prevalent as applications become increasingly more complex. However, current DSP C compilers are generally unable to exploit numerous DSP specific architectural features when attempting to produce efficient assembly code. Therefore, in order to respect tight real-time constraints, programmers commonly write DSP code by hand. However, the programming of such code in assembly language has become increasingly difficult since DSP applications are becoming larger and more complex. Furthermore, the writing of efficient assembly code for new DSP architectures, such as for a Very Long Instruction Word (VLIW) processor, presents a very challenging task.
SUMMARY OF THE INVENTION
A tool is provided for estimating an optimized assembly code from the C code of an application. An ability is provided to locate computationally intensive parts of the application. Furthermore, the tool provides a metric of the quality of the produced assembly code. More particularly, an estimation of a hand-written assembly code is generated from an intermediate description (RTL) of an application.
According to one aspect, a performance evaluation apparatus is provided for annotating by priority level a DSP intermediate representation (DIR) of an application source code. The DIR includes nodes, leaf nodes and heading nodes, wherein the heading nodes represent data ready operations. The apparatus includes a host computer, a target digital signal processor (DSP) compiler, and a DSP Intermediate Representation (DIR) annotation algorithm. The host computer includes processing circuitry, memory and a host compiler to use test sequences and generate dynamic information. The target digital signal processor compiler communicates with the processing circuitry. The DSP Intermediate Representation (DIR) annotation algorithm is implemented on the host processing circuitry and is operative to annotate application source code by giving priority to operations that allow more distant leaf nodes to be scheduled earlier. Accordingly, nodes with high priority levels are scheduled first, enabling target DSP pipeline parallelism to be extracted.
According to another aspect, a performance evaluation apparatus is provided for annotating by priority level a DSP intermediate representation (DIR) of an application source code. The DIR includes nodes, leaf nodes and heading nodes, wherein the heading nodes represent data ready operations. The apparatus includes a host computer, a target DSP compiler, and an annotation algorithm. The host computer includes processing circuitry, memory and a host compiler. The host compiler is operative to execute the program using test sequences and generate dynamic information. The target digital signal processor (DSP) compiler communicates with the processing circuitry. The annotation algorithm is implemented on the host processing circuitry and is operative to annotate application source code by giving priority to operations that allow more distant nodes to be scheduled earlier such that nodes with high priority levels are scheduled first, enabling target DSP pipeline parallelism to be extracted.
According to yet another aspect, a method is provided for annotating a DSP Intermediate Representation (DIR) for a program source code. The method includes: providing an application C source code; generating a DIR of the application C source code suitable to estimate a class of modified Harvard DSP architectures; calculating a priority level comprising a cycle-based distance between a node and a most distant leaf node of the DIR; and annotating each node of the DIR by the calculated priority level.
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Pegatoquet, Alain et al, Rapid Development of Optimized DSP Code from a High Level Description Through Software Estimations, Proceedings of the 36th Conference on Design Automation, New Orleans, LA, USA, Jun. 21-25, 1999. ACM Press, 1999, pp. 823-826.*
Wilken, Kent et al, Optimal instruction scheduling using integer programming, Conference on Programming Language Design and Implementation, Proceedings of the ACM SIGPLAN 2000 conference on Programming language design and implementation, 2000, Vancouver.*
Akturan, Cagdas, et al, FDRA: a software-pipelining algorithm for embedded VLIW processors, International Symposium on Systems Synthesis, Proceedings of the 13th international symposium on System synthesis, 2000, Madrid, Spain, ACM Press, New York, NY, US.
Auguin Michel
Pegatoquet Alain
Sohier Olivier
Koninklijke Philips Electronics , N.V.
Starks, Jr. Wilbert L.
Zawilski Peter
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