Patent
1999-01-29
2000-02-08
Teska, Kevin J.
39550034, G06F 1750
Patent
active
06023573&
ABSTRACT:
A method and apparatus for generating and analyzing reduced-order models of linear circuits. The method and apparatus generates a characteristic tridiagonal matrix using a look-ahead Lanczos procedure and then checks the matrix for stability and passivity. If the matrix is not stable and passive, the matrix is modified via a partial Pade via Lanczos approximation algorithm and then rechecked for passivity and stability. The process is iterated until a passive and stable model is generated. When a satisfactory matrix is generated, a Pade approximant of a transfer function of the circuit is computed and the frequency response of this circuit is generated and displayed.
REFERENCES:
patent: 5163015 (1992-11-01), Yokota
patent: 5313398 (1994-05-01), Rohrer et al.
patent: 5379231 (1995-01-01), Pillage et al.
patent: 5469366 (1995-11-01), Yang et al.
patent: 5537329 (1996-07-01), Feldmann et al.
patent: 5629845 (1997-05-01), Liniger
patent: 5689685 (1997-11-01), Feldmann et al.
"Reduced-Order Modeling of Large Linear Subcircuits via a Block Lanczos Algroithm", P. Feldmann and R.W. Freund, Copyright 1995, IEEE Catalog No. 95CH35812. No p #s.
"Reduced-Order Modeling of Large Passive Linear Circuits by Means of the SyPVL Algorithm", R.W. Freund and P. Feldmann, Copyright 1996, IEEE. No p #s.
Bai Zhaojun
Feldmann Peter
Freund Roland W.
Garbowski Leigh Marie
Lucent Technologies - Inc.
Teska Kevin J.
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