Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
1999-03-11
2001-04-17
Ngo, Ngan V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S531000, C257S532000, C257S700000, C257S724000
Reexamination Certificate
active
06218729
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The invention relates generally to semiconductor device packages and more specifically to fabricating high Q reactive components in such packages.
BACKGROUND ART
The present invention relates to the construction of high Q passive devices, typically used for example in radio frequency applications. Such devices are notoriously difficult to incorporate in the semiconductor die because of various factors: The quality factor (Q) of both lumped and distributed reactive components is primarily determined by the resistance of the metal, dielectric losses and parasitic reactances. The actual inductive and capacitive values in lumped components is greatly limited by the available area on the semiconductor die. Similarly, distributed transmission line resonators are difficult to configure on a semiconductor die for desired frequencies also because of space limitations. The usual practice is to place the lumped reactances on the PC board. However, the parasitic reactances associated with conventional package technologies often seriously degrade the performance of a functional circuit. For example, in power amplifier applications, the parasitic reactance of the package leads often approaches or exceeds the output impedance of the active semiconductor device. In many cases, the package reactance negates the possibility of building acceptable power amplifiers on silicon or silicon-germanium processes. Similar arguments can be cited for small signal applications as well.
Integrated circuits are typically mounted in plastic or ceramic packages that connect the semiconductor die to leads or balls which are subsequently soldered to a PCB. Some package types contain multiple metal layers, e.g. a flip-chip ball-grid array, in order to route the I/O pads and utility pads to the external contacts of the package.
FIG. 11
, for example, shows a typical ball-grid package. A semiconductor die
1102
is mounted to a substrate
1112
is secured thereto by an underfill epoxy compound
1106
. The substrate includes a set of metal interconnect layers to provide an electrical pathway between the solder balls (or “bumps”)
1104
of the die and the solder balls
1114
of the substrate. An overmold epoxy
1110
is used to encapsulate the die, thus completing the ball-grid package.
FIG. 12
is an enlarged view of a portion of substrate
1112
, identified in FIG.
11
. It can be seen that the substrate consists of a laminated structure of alternating layers of metal
1212
. These metal layers are insulated from each other by layers of insulating material
1210
such as epoxy or ceramic. These metal layers provide interconnections among or between the bonding pads or “bumps” on the semiconductor die
1102
. The metal layers are patterned with interconnects (not shown) and vias
1202
which provide interconnectivity among the metal layers.
What is needed is a scheme for providing high Q components in IC devices without having to use discrete components. It is desirable to incorporate such devices within the IC device itself, and thus save space on the PCB while at the same time gaining the advantages made possible by the use of high Q components.
SUMMARY OF THE INVENTION
In accordance with the invention, an improved IC packaging scheme includes incorporation of passive devices in the packaging of the IC. An IC mounting substrate carries the semiconductor die and has a laminated structure of metal interconnects for providing external contacts to the I/O pads of the die and utility pads such as power and ground. Designed into the metal interconnect layers, are passive devices which connect with the traces comprising the interconnects, directly or by way of vias, to provide additional electrical functionality to the semiconductor die. Therefore desired reactive components are fabricated from the package metal layers proper. Resistance is greatly reduced since the package metal is typically 20 microns thick compared to on-chip metal which is typically less than one micron thick. Typical applications include, but are not limited to filter circuits for filtering input or output signals, power supply bypass capacitors, impedance matching circuits, resonators, and so on. The invention is also applicable in multi-chip modules where two or more semiconductor dice are packaged in a single IC package. Passives could be used to couple signals going between the dice.
A method of fabricating the substrate of the present invention includes depositing insulative layers and metal layers. Each metal layer is patterned and treated to a photoresist etch step. The patterning includes defining the traces which constitute the interconnects. The structures which constitute the passives are patterned at the same time as the interconnects. No additional metal is consumed, since the structures for the passives are patterned from the same metal layer as for the interconnects; the only difference is that less metal is etched away.
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Baumann Dan C.
Zavrel, Jr. Robert J.
Atmel Corporation
McGuire, Jr. John P.
Ngo Ngan V.
Schneck Thomas
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